Patent application number | Description | Published |
20080309396 | Hacking Detector Circuit For Semiconductor Integrated Circuit and Detecting Method Thereof - Disclosed is a semiconductor integrated circuit which includes a pre-charge capacitor connected to a check node pre-charged. A sense capacitor is configured to discharge the check node. A detector is configured to detect whether the sense capacitor is exposed, based upon a voltage of the check node after a predetermined length of time has elapses. | 12-18-2008 |
20090010071 | NONVOLATILE MEMORY DEVICE AND ERASING METHOD - Disclosed is an erasing method for a nonvolatile memory device that includes erasing selected memory cells and erase-verifying the selected memory cells after increasing their threshold voltage by application of a negative bulk bias voltage. | 01-08-2009 |
20100124123 | Nonvolatile Memory Device with Incremental Step Pulse Programming - A nonvolatile memory device includes a sense amplifier circuit sensing first data from a memory cell via a bit line and outputting the sensed first data, in response to a read command. A write driver circuit programs the memory cell and stores second data indicating a programming state of the memory cell, in response to a program command. A verification block outputs a result of a comparison between the first and second data in response to a first read command. The second data is updated based on the determination on the programming of the memory cell in response to a second read command applied following the first read command. | 05-20-2010 |
20100232227 | NON-VOLATILE MEMORY DEVICE AND PROGRAM METHOD THEREOF - A non-volatile memory device including a memory cell array; a read/write circuit configured to drive bit lines of the memory cell array with a negative bit line voltage according to data to be programmed; a bit line setup-time measuring circuit configured to measure the bit line setup-time, which may be a function of the amount of data to be programmed, at each ISPP program loop; and a control logic configured to control the program voltage and/or the applied time of a program voltage applied to the selected wordline of the memory cell array based on the measured bit line setup-times measured at each ISPP program loop. | 09-16-2010 |
20100241877 | IC CARD WITH PARALLEL ACCESSED MEMORY BLOCKS - Disclosed is an integrated circuit card which includes a central processing unit (CPU); a first memory block and a second memory block configured to operate responsive to a control of the CPU; and a high voltage generator block configured to generate a high voltage to be supplied to the first and second memory blocks. When bit lines of the first memory block are set by the high voltage, the CPU controls the high voltage generator block to supply the second memory block with the high voltage for a program operation of the second memory block during the program operation of the first memory block. | 09-23-2010 |
20100323799 | SERVICE PROVIDING METHOD USING ON-LINE GAME, AND RECORDING MEDIA RECORDING PROGRAM FOR IMPLEMENTING THE METHOD - An approach is provided for providing a service using an on-line game capable of, maximizing effects of services associated with the on-line game, and recording media recording a program for implementing the service providing method. The service providing method may include, for example, storing, in a rendering region, game object drawing information of a game screen for the on-line game in response to a request for reproducing the game screen; hooking the rendering region to change the game object drawing information so that service object information provided from a game server is included in the game object drawing information; storing the changed game object drawing information in the rendering region; and providing the game screen by rendering the game object drawing information including the service object information stored in the rendering region. | 12-23-2010 |
20110101114 | Memory System and Data Reading Method Thereof - A memory system includes a memory and a memory controller operating to control the memory. The memory includes a random accessible memory including a memory cell array operable in a random access mode, a NAND flash memory, and a selection circuit making the memory controller operate either one of the random accessible memory or the NAND flash memory. | 05-05-2011 |
20110225351 | MEMORY CARD AND MEMORY SYSTEM HAVING THE SAME - A memory card includes: a first memory chip responding to all commands input externally; and a second memory chip responding to commands, among the commands input externally, relevant to reading, programming, and erasing operations with data. Card identification information stored in the first memory chip includes capacity information corresponding to a sum of sizes of the first and second memory chips. The plurality of memory chips of the memory card are useful in designing the memory card with storage capacity in various forms. | 09-15-2011 |
20120300548 | MEMORY SYSTEM AND DATA READING METHOD THEREOF - A memory system includes a memory and a memory controller operating to control the memory. The memory includes a random accessible memory including a memory cell array operable in a random access mode, a NAND flash memory, and a selection circuit making the memory controller operate either one of the random accessible memory or the NAND flash memory. | 11-29-2012 |
20130316825 | SERVICE PROVIDING METHOD USING ON-LINE GAME, AND RECORDING MEDIA RECORDING PROGRAM FOR IMPLEMENTING THE METHOD - An approach is provided for providing a service using an on-line game capable of, maximizing effects of services associated with the on-line game, and recording media recording a program for implementing the service providing method. The service providing method may include, for example, storing, in a rendering region, game object drawing information of a game screen for the on-line game in response to a request for reproducing the game screen; hooking the rendering region to change the game object drawing information so that service object information provided from a game server is included in the game object drawing information; storing the changed game object drawing information in the rendering region; and providing the game screen by rendering the game object drawing information including the service object information stored in the rendering region. | 11-28-2013 |