Patent application number | Description | Published |
20090278592 | INTERNAL VOLTAGE DISCHARGE CIRCUIT AND ITS CONTROL METHOD - An internal voltage discharge circuit includes a differential comparator for differentially comparing a reference voltage with a feedback voltage to generate a discharge control voltage, a level detector for detecting a level of external power supply voltage and a discharge unit for adjusting an amount of discharge of an internal voltage based on the level signal detected by the level detector and the discharge control voltage from the differential comparator. | 11-12-2009 |
20100039143 | OUTPUT CIRCUIT AND DRIVING METHOD THEREOF - An output circuit includes a pre-driving unit configured to drive an input signal by using a different driving power according to an output operation mode and generate pull-up and pull-down signals corresponding to the resultant input signal and an output driving unit configured to output data in response to the pull-up and pull-down signals. | 02-18-2010 |
20100039873 | SENSE AMPLIFIER DRIVING CONTROL CIRCUIT AND METHOD - A sense amplifier driving control circuit has a stable discharge characteristic by differently controlling the discharge of a node having a driving voltage according to the change of an organization of a semiconductor memory device. The sense amplifier driving control circuit includes a pull-down driving block configured to provide a pull-down voltage for a pull-down operation of the sense amplifier, a pull-up driving block configured to sequentially provide a first voltage for the overdrive and a second voltage for the normal drive as a pull-up voltage for a pull-up operation of the sense amplifier, wherein a voltage level of the second voltage is lower than that of the first voltage, and a discharging block configured to discharge the node having the second voltage by controlling a amount of the discharging according to an organization of the semiconductor memory device. | 02-18-2010 |
20120169370 | SYSTEM AND PACKAGE INCLUDING PLURAL CHIPS AND CONTROLLER - A system includes an input/output channel and a plurality of chips coupled to the input/output channel, wherein only one chip of the plurality of chips performs a termination operation for impedance matching of the input/output channel. | 07-05-2012 |
20120170383 | INTEGRATED CIRCUIT, SYSTEM INCLUDING THE SAME, MEMORY, AND MEMORY SYSTEM - A system includes integrated circuit chip including a first buffer configured to receive signals and a second buffer configured to receive signals, wherein the first buffer receives signals of a higher frequency than the second buffer, a controller chip configured to control the integrated circuit chip, an I/O channel formed between the controller chip and the integrated circuit chip to transfer a first signal and a second speed signal, wherein the first signal has a higher frequency than the second signal, and a status channel formed between the controller chip and the integrated circuit chip to transfer at least one status signal, wherein the integrated circuit chip is configured to select one of the first buffer and the second buffer and actives the selected buffer in response to the at least one status signal and receive a signal transferred through the I/O channel. | 07-05-2012 |
20120170384 | INTEGRATED CIRCUIT, MEMORY SYSTEM, AND OPERATION METHOD THEREOF - An integrated circuit includes an input pad configured to receive a low-speed signal and a high-speed signal, a high-speed buffer coupled to the input pad, a low-speed buffer coupled to the input pad, a strobe input unit configured to receive a strobe signal for indicating an input of the high-speed signal to the input pad, and a buffer control unit configured to control an activation of the high-speed buffer in response to the strobe signal. | 07-05-2012 |
20120170593 | SYSTEM INCLUDING CHIPS, INTEGRATED CIRCUIT CHIP, AND METHOD FOR TRANSMITTING DATA PACKET - A method for transmitting a data packet includes transmitting the data packet at a first frequency during an initial period for transmitting the data packet and transmitting the data packet at a second frequency different from the first frequency after the initial period. | 07-05-2012 |
20120170671 | INTEGRATED CIRCUIT CHIP, SYSTEM INCLUDING MASTER CHIP AND SLAVE CHIP, AND OPERATION METHOD THEREOF - An integrated circuit chip includes: a plurality of input pads; a plurality of first buffers respectively coupled with the input pads; and a plurality of second buffers respectively coupled with the input pads, wherein the first buffers are configured to receive signals of a higher frequency than the second buffer, wherein the second buffers and the first buffers are configured to selectively output the signals input to the selected buffers according to an operation mode that is set in response to an input signal. | 07-05-2012 |
20130099830 | INTEGRATED CIRCUIT CHIP - An integrated circuit chip includes a first single ended type buffer configured to receive a first signal through a first pad, a second single ended type buffer configured to receive a second signal through a second pad, a differential type buffer configured to receive a third signal through the first pad and the second pad, a strobe input unit configured to receive a strobe signal synchronized with the third signal inputted to the first pad and the second pad, and a buffer control unit configured to control activation of the first and second single ended type buffers and the differential type buffer in response to the strobe signal. | 04-25-2013 |
20130099833 | INTEGRATED CIRCUIT CHIP AND SYSTEM HAVING THE SAME - An integrated circuit chip includes: an internal circuit; a data output circuit configured to output a data packet of the internal circuit in response to a strobe signal; an oscillator configured to generate a first clock signal; a divider configured to divide the first clock signal and generate a second clock signal; and a strobe signal supply unit configured to supply the second clock signal as the strobe signal during an initial period of transmission of the data packet and supply the first clock signal as the strobe signal after the initial period. | 04-25-2013 |
20130103868 | INTEGRATED CIRCUIT SYSTEM AND METHOD FOR OPERATING MEMORY SYSTEM - An integrated circuit system includes: a master chip; a slave chip configured to operate under a control of the master chip; and a data channel configured to transfer data between the master chip and the slave chip, wherein a data transfer rate from the master chip to the slave chip through the data channel is different from a data transfer rate from the slave chip to the master chip through the data channel. | 04-25-2013 |
20130215569 | INTEGRATED CIRCUIT CHIP, MOBILE DEVICE INCLUDING THE SAME, AND METHOD FOR OPERATING THE MOBILE DEVICE - A mobile device includes a docking unit for docking with an external device, and an integrated circuit chip including an impedance matching circuit for impedance matching of an internal bus outside of the integrated circuit chip, wherein activation or deactivation of the impedance matching circuit is determined based on whether the docking unit is docked. | 08-22-2013 |
20130258778 | READ VOLTAGE GENERATION CIRCUIT, MEMORY AND MEMORY SYSTEM INCLUDING THE SAME - A read voltage generation circuit includes a register unit configured to store an initial read voltage code, a counter circuit configured to change a read voltage code in every read-retry operation, wherein an initial value of the read voltage code is the initial read voltage code; and a voltage generation circuit configured to generate a read voltage corresponding to a read voltage code produced by the counter circuit. | 10-03-2013 |
20140111254 | INTEGRATED CIRCUIT CHIP AND SYSTEM HAVING THE SAME - An integrated circuit chip includes: an internal circuit; a data output circuit configured to output a data packet of the internal circuit in response to a strobe signal; an oscillator configured to generate a first clock signal; a divider configured to divide the first clock signal and generate a second clock signal; and a strobe signal supply unit configured to supply the second clock signal as the strobe signal during an initial period of transmission of the data packet and supply the first clock signal as the strobe signal after the initial period. | 04-24-2014 |
20140111255 | INTEGRATED CIRCUIT CHIP AND SYSTEM HAVING THE SAME - An integrated circuit chip includes: an internal circuit; a data output circuit configured to output a data packet of the internal circuit in response to a strobe signal; an oscillator configured to generate a first clock signal; a divider configured to divide the first clock signal and generate a second clock signal; and a strobe signal supply unit configured to supply the second clock signal as the strobe signal during an initial period of transmission of the data packet and supply the first clock signal as the strobe signal after the initial period. | 04-24-2014 |