Patent application number | Description | Published |
20090251181 | Method and apparatus for tuning phase of clock signal - A method and apparatus for tuning a phase of a data clock signal having a different frequency than a main clock signal. The method of tuning includes coarse tuning by receiving the data clock signal, dividing the data clock signal to generate a frequency-divided clock signal having a same frequency as the main clock signal, repeatedly shifting the frequency-divided clock signal to generate multiphase frequency-divided clock signals at a predetermined phase interval, comparing a phase of each of the multiphase frequency-divided clock signals with a phase of the main clock signal, and determining a phase shift amount based on a comparison result, and fine tuning by comparing a phase of a multiphase frequency-divided clock signal corresponding to the phase shift amount with the phase of the main clock signal and adjusting the phase of the data clock signal by a predetermined phase step based on the comparison result. | 10-08-2009 |
20100079180 | AC-COUPLING PHASE INTERPOLATOR AND DELAY-LOCKED LOOP USING THE SAME - An AC-coupling phase interpolator and a DLL using the same are provided. The AC-coupling phase interpolator includes a coupling capacitor generating and outputting a coupling signal by AC-coupling to an interpolation signal obtained by phase-interpolating an input signal. Thereby, it is possible to correct duty of an input signal and adjust the level of an output signal. | 04-01-2010 |
20100103952 | Method, device, and system for data communication with preamble for reduced switching noise - A data communication device or system includes a preamble unit and a data interface. The preamble unit generates or detects a first preamble having a first length for a first data line, and generates or detects a second preamble having a second length for a second data line. The first length is different from the second length, and data on the first and second data lines form parallel data. The data interface communicates a first data with the first preamble via the first data line and communicates a second data with the second preamble via the second data line. The respective length and/or respective pattern of each preamble are adjustable and/or programmable. | 04-29-2010 |
20100141311 | Phase-Locked Loop and Bias Generator - A phase-locked loop (PLL) having a bias generator capable of reducing noise is provided. In the PLL, a voltage controlled oscillator is driven using a regulator. The bias generator, which applies a bias voltage to the regulator, is configured to have opposite power noise characteristics to the power noise characteristics of the regulator, such that the occurrence of jitter in the PLL is reduced. | 06-10-2010 |
20100259310 | DATA TRANSFER CIRCUIT AND METHOD WITH COMPENSATED CLOCK JITTER - A data I/O interface for an integrated circuit device includes a noise detector receiving a power supply voltage, detecting a power supply voltage noise component, and providing a clock delay control signal in response to detected power supply voltage noise component. The data I/O interface also includes a clock delay circuit providing a delayed clock signal in response to the clock delay control signal, and a data transfer circuit powered by the power supply voltage and providing output data synchronously with the delayed clock signal. | 10-14-2010 |
20100271887 | SEMICONDUCTOR MEMORY DEVICE COMPRISING VARIABLE DELAY UNIT - A semiconductor memory device comprises a variable delay unit and a data trainer. The variable delay unit is configured to generate a write data signal by delaying a write data driving signal by different amounts of time depending on whether the semiconductor memory device is in a data training mode or a normal operating mode, and further configured to generate a read data driving signal by delaying a read data signal by different amounts of time in the data training mode and the normal operating mode. The data trainer is configured to be activated in the data training mode, and while activated, receive the write data signal, compare the write data signal with a predetermined write pattern, perform a data training mode operation, and output the read data signal with a predetermined read pattern. | 10-28-2010 |
20100329041 | SEMICONDUCTOR MEMORY DEVICE HAVING POWER-SAVING EFFECT - A semiconductor memory device includes a memory cell array, a controller, and a data input/output (I/O) unit. The memory cell array includes a plurality of memory cells and is configured to store data. The controller is configured to enable a write clock signal in response to an active command when a write latency of the semiconductor device is less than a reference write latency and disable the write clock signal during a disabling period in which read data is output from the semiconductor device. The data I/O unit is configured to receive data in response to the write clock signal and output the data to the memory cell array. | 12-30-2010 |
20110026334 | BIDIRECTIONAL EQUALIZER WITH CMOS INDUCTIVE BIAS CIRCUIT - An integrated circuit (IC) device, system and related method of communicating data are described. The IC device includes; a data port configured to provide output data to a channel and receive input data from the channel, an impedance matching circuit connected to the data port and configured to operate as an output driver circuit when the output data is being transmitted and as an on die termination circuit when the input data is being received, and an active inductive bias circuit connected to the data port in parallel with the impedance matching circuit, and configured to adjust the impedance of the data port to the channel during transmission of the output data as a function of output data frequency and adjust the impedance of the data port to the channel during receipt of the input data as a function of input data frequency. | 02-03-2011 |
20110030064 | DATA MASK SYSTEM AND DATA MASK METHOD - A data mask system includes a processor providing control signals including a command signal, an address signal, and a data signal, a data mask processor receiving the control signals and providing either write data or masked data in response to the control signals, and generating data mask information and a data mask selection signal from at least one of the control signals, and a data mask register unit receiving the data mask selection signal, storing the data mask information, selecting a subset of the stored data mask information in response to the data mask selection signal, and returning selected data mask information to the data mask processor. The data mask processor receives the selected data mask information from the data mask register unit and provides the masked data as a result of performing a data mask operation on the data signal according to the selected data mask information. | 02-03-2011 |
20110156934 | METHOD AND APPARATUS FOR PARALLEL DATA INTERFACING USING COMBINED CODING AND RECORDING MEDIUM THEREFOR - A semiconductor device may include a coding lookup table unit including a plurality of coding lookup tables each of which is selected by a respectively selection signal, and a selection unit configured to receive one of N-bit parallel data and extract respective encoded data corresponding to the selection signal and to which the N-bit parallel data is mapped from the coding lookup table unit, and encoded data and extract respective N-bit parallel data corresponding to the selection signal and to which the encoded data is mapped from the coding lookup table unit, wherein N is 2 or an integer greater than 2, and wherein the coding lookup tables respectively store a plurality of coded data patterns that respectively correspond to patterns of the N-bit parallel data and are random temporally and spatially. | 06-30-2011 |
20110158011 | SEMICONDUCTOR MEMORY INTERFACE DEVICE AND METHOD - A memory interface circuit is provided, comprising: a first signal output circuit configured to output a first signal via a first signal line to a first I/O terminal; a second signal output circuit configured to output a second signal via a second signal line to a second I/O terminal; and a noise cancellation circuit having at least one phase adjusting element and at least one gain adjusting element to reduce a noise signal induced on the second signal line due to the presence of the first signal on the first signal line, wherein the second signal line is disposed adjacent to the first signal line. | 06-30-2011 |
20110158030 | METHOD AND APPARATUS FOR TUNING PHASE OF CLOCK SIGNAL - A method and apparatus for tuning a phase of a data clock signal having a different frequency than a main clock signal. The method of tuning includes coarse tuning by receiving the data clock signal, dividing the data clock signal to generate a frequency-divided clock signal having a same frequency as the main clock signal, repeatedly shifting the frequency-divided clock signal to generate multiphase frequency-divided clock signals at a predetermined phase interval, comparing a phase of each of the multiphase frequency-divided clock signals with a phase of the main clock signal, and determining a phase shift amount based on a comparison result, and fine tuning by comparing a phase of a multiphase frequency-divided clock signal corresponding to the phase shift amount with the phase of the main clock signal and adjusting the phase of the data clock signal by a predetermined phase step based on the comparison result. | 06-30-2011 |
20110170620 | Method, Device, and System for Data Communication with Preamble for Reduced Switching Noise - A data communication device or system includes a preamble unit and a data interface. The preamble unit generates or detects a first preamble having a first length for a first data line, and generates or detects a second preamble having a second length for a second data line. The first length is different from the second length, and data on the first and second data lines form parallel data. The data interface communicates a first data with the first preamble via the first data line and communicates a second data with the second preamble via the second data line. The respective length and/or respective pattern of each preamble are adjustable and/or programmable. | 07-14-2011 |
20110242916 | ON-DIE TERMINATION CIRCUIT, DATA OUTPUT BUFFER AND SEMICONDUCTOR MEMORY DEVICE - An on-die termination circuit includes a termination resistor unit connected to an external pin, and a termination control unit connected to the termination resistor unit. The termination resistor unit provides termination impedance to a transmission line connected to the external pin. The termination control unit varies the termination impedance in response to a plurality of bits of strength code associated with a data rate. | 10-06-2011 |
20110242924 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor memory device includes a memory cell array, an address control unit and a logic circuit. The memory cell array includes a plurality of banks which are divided into a first bank block and a second bank block. The address control unit accesses the memory cell array. The logic circuit controls the address control unit based on a command and an address signal such that the first and second bank blocks commonly operate in a first operation mode, and the first and second bank blocks individually operate in a second operation mode. | 10-06-2011 |
20110243289 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - A method of tuning a phase of a clock signal includes performing data training on a plurality of data pins through which data are input and output, in synchronization with a data clock signal; determining one of the data pins to be a representative pin; performing clock and data recovery (CDR) on read data of the representative pin; and adjusting a phase of the data clock signal based on the CDR. | 10-06-2011 |
20110246857 | MEMORY SYSTEM AND METHOD - A memory system includes a memory controller and a memory device. The memory device exchanges data through a first channel with the memory controller, exchanges a first cyclic redundancy check (CRC) code associated with the data through a second channel with the memory controller, and receives a command/address packet including a second CRC code associated with a command/address from the memory controller through a third channel. | 10-06-2011 |
20110292742 | Stacked Semiconductor Memory Device, Memory System Including The Same, And Method Of Repairing Defects Of Through Silicon Vias - A stacked semiconductor memory device according to the inventive concepts may include a plurality of memory chips stacked above a processor chip, a plurality of TSVs, and I/O buffers. The TSVs may pass through the memory chips and are connected to the processor chip. I/O buffers may be coupled between all or part of the memory chips and the TSVs and may be selectively activated on the basis of defective states of the TSVs. | 12-01-2011 |
20110298499 | INTERNAL VOLTAGE GENERATOR AND INTEGRATED CIRCUIT DEVICE INCLUDING THE SAME - An internal voltage generator includes a comparison unit, a driving circuit and a bias unit. The comparison unit compares a reference voltage and an internal voltage and is configured to output a comparison voltage, which is based on a difference between the reference voltage and the internal voltage. The driving circuit receives the comparison voltage and an external power supply voltage and is configured to output the internal voltage to an output node in response to the comparison voltage. The bias unit receives the internal voltage and is configured to adaptively adjust a bias current that flows through the bias unit to drive the comparison unit, in consideration of a level of the internal voltage. | 12-08-2011 |
20110309468 | SEMICONDUCTOR CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor chip package includes a substrate, a first layer disposed on the substrate and a second layer substantially similar to and disposed on the first layer. The first layer has a first input/output (I/O) circuit, a first through-via connected to the first input/output (I/O) circuit and a second through-via that is not connected to the first I/O circuit. The second layer has a second I/O circuit, a third through-via connected to the second I/O circuit and a fourth through-via that is not connected to the second I/O circuit. The first through-via is connected to the fourth through-via, and the second through-via is connected to the third through-via. The package maybe fabricated by stacking the layers, and changing the orientation of the second layer relative to the first to ensure that the first through-via is connected to the fourth through-via, and the second through-via is connected to the third through-via. | 12-22-2011 |
20110310659 | VOLTAGE-CONTROLLED OSCILLATOR AND PHASE-LOCKED LOOP CIRCUIT - A voltage-controlled oscillator includes an oscillating unit configured to output first and second output clock signals at first and second nodes, respectively, the first and second output clock signals having a frequency that is variable in response to a control voltage. An active element unit connected to the oscillating unit is configured to maintain oscillation of the oscillating unit. A bias current generating unit connected to the active element unit at a bias node provides a bias current to the bias node and is adapted to adjust the bias current in response to a control code. First and second capacitor blocks connected to the oscillating unit and the active element unit provide first and second load capacitances, respectively, to the first and second nodes, respectively, in response to the control code. | 12-22-2011 |
20120063242 | DATA RECEIVER AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A data receiver in a memory device includes an integration unit, a sense amplification unit and a latch unit. The integration unit integrates a data signal to generate a first equalization signal in response to a sampling feedback signal. The data signal includes a plurality of data that are sequentially received. The sense amplification unit senses the first equalization signal to generate a second equalization signal in response to a sensing feedback signal. The latch unit latches the second equalization signal to generate a sampling data signal | 03-15-2012 |
20120086490 | INTEGRATED CIRCUIT DEVICES USING POWER SUPPLY CIRCUITS WITH FEEDBACK FROM A REPLICA LOAD - An integrated circuit device includes an external power supply input configured to be coupled to an external power supply and a digital circuit, such as a clock signal generator circuit, that generates noise at a power supply input thereof. The device further includes a replica load circuit and a power supply circuit coupled to the external power supply input, to a power supply input of the digital circuit and to a power supply input of the replica load circuit. The power supply circuit is configured to selectively couple the external power supply node to the power supply input of the digital circuit responsive to a voltage at the power supply input of the replica load circuit. The replica load circuit may be configured to provide a load that varies responsive to a voltage at the power supply input of the digital circuit. | 04-12-2012 |
20120087194 | DATA WRITE TRAINING METHOD AND SEMICONDUCTOR DEVICE PERFORMING THE SAME - Embodiments may be directed to a method of operating a semiconductor device, the method including receiving a first write training command, receiving a first write data responsive to the first write training command through a first data line, and transmitting the first write data through a second data line. Transmitting the first write data is performed without an additional training command. | 04-12-2012 |
20120099383 | DATA OUTPUT BUFFER AND MEMORY DEVICE - A data output buffer includes a driving unit and a control unit. The driving unit selectively performs a termination operation that provides a termination impedance to a transmission line coupled to an external pin, and a driving operation that provides a drive impedance to the transmission line while outputting read data. The control unit adjusts a value of the termination impedance and a value of the drive impedance based on an output voltage at the external pin during a termination mode, and controls the driving unit to selectively perform one of the termination operation and the driving operation during a driving mode. | 04-26-2012 |
20130009685 | DATA TRANSFER CIRCUIT AND METHOD WITH COMPENSATED CLOCK JITTER - A data I/O interface for an integrated circuit device includes a noise detector receiving a power supply voltage, detecting a power supply voltage noise component, and providing a clock delay control signal in response to detected power supply voltage noise component. The data I/O interface also includes a clock delay circuit providing a delayed clock signal in response to the clock delay control signal, and a data transfer circuit powered by the power supply voltage and providing output data synchronously with the delayed clock signal. | 01-10-2013 |
20130054904 | DATA MASK SYSTEM AND DATA MASK METHOD - A data mask system includes a processor providing control signals including a command signal, an address signal, and a data signal, a data mask processor receiving the control signals and providing either write data or masked data in response to the control signals, and generating data mask information and a data mask selection signal from at least one of the control signals, and a data mask register unit receiving the data mask selection signal, storing the data mask information, selecting a subset of the stored data mask information in response to the data mask selection signal, and returning selected data mask information to the data mask processor. The data mask processor receives the selected data mask information from the data mask register unit and provides the masked data as a result of performing a data mask operation on the data signal according to the selected data mask information. | 02-28-2013 |
20130208546 | LATENCY CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE COMPRISING SAME - A latency control circuit is configured to delay a read information signal in response to a CAS latency signal and an internal clock signal to generate a delayed read information signal, and is further configured to generate a latency control signal based on the delayed read information signal in response to a plurality of sampling control signals and a plurality of transfer control signals. | 08-15-2013 |
20130235683 | DATA WRITE TRAINING METHOD - Embodiments may be directed to a method of operating a semiconductor device, the method including receiving a first write training command, receiving a first write data responsive to the first write training command through a first data line, and transmitting the first write data through a second data line. Transmitting the first write data is performed without an additional training command. | 09-12-2013 |
20140019833 | MEMORY SYSTEM AND METHOD - A memory system includes a memory controller and a memory device. The memory device exchanges data through a first channel with the memory controller, exchanges a first cyclic redundancy check (CRC) code associated with the data through a second channel with the memory controller, and receives a command/address packet including a second CRC code associated with a command/address from the memory controller through a third channel. | 01-16-2014 |
20140032826 | METHOD OF TRAINING MEMORY CORE AND MEMORY SYSTEM - A method of training a memory device included in a memory system is provided. The method includes testing memory core parameters for a memory core of the memory device during a booting-up sequence of the memory system; determining trimmed memory core parameters based on the test results; storing the determined trimmed memory core parameters; and applying the trimmed memory core parameter to the memory device during a normal operation of the memory device. | 01-30-2014 |
20140035765 | METHOD AND APPARATUS FOR PARALLEL DATA INTERFACING USING COMBINED CODING AND RECORDING MEDIUM THEREFOR - A semiconductor device may include a coding lookup table unit including a plurality of coding lookup tables each of which is selected by a respectively selection signal, and a selection unit configured to receive one of N-bit parallel data and extract respective encoded data corresponding to the selection signal and to which the N-bit parallel data is mapped from the coding lookup table unit, and encoded data and extract respective N-bit parallel data corresponding to the selection signal and to which the encoded data is mapped from the coding lookup table unit, wherein N is 2 or an integer greater than 2, and wherein the coding lookup tables respectively store a plurality of coded data patterns that respectively correspond to patterns of the N-bit parallel data and are random temporally and spatially. | 02-06-2014 |
20140089574 | SEMICONDUCTOR MEMORY DEVICE STORING MEMORY CHARACTERISTIC INFORMATION, MEMORY MODULE AND MEMORY SYSTEM HAVING THE SAME, AND OPERATING METHOD OF THE SAME - A semiconductor memory device storing memory characteristic information, a memory module including the semiconductor memory device, a memory system, and an operating method of the semiconductor memory device. The semiconductor memory device may include a cell array including a plurality of areas; a command decoder configured to decode a command and generate an internal command; and an information storage unit configured to store characteristic information of at least one of the plurality of areas. When a first command and a first row address accompanying the first command are received, characteristic information of an area corresponding to the first row address is provided to an outside. | 03-27-2014 |
20140108716 | DYNAMIC RANDOM ACCESS MEMORY FOR STORING RANDOMIZED DATA AND METHOD OF OPERATING THE SAME - A dynamic random access memory (DRAM) includes a memory cell array, a data input/output circuit, and a data randomizer configured to randomize data to be stored in the memory cell array. The data randomizer includes an encoder configured to generate write data by encoding input data received from the data input/output circuit using a randomization code and to output the write data to the memory cell array. The data randomizer further includes a decoder configured to generate output data by decoding read data received from the memory cell array using the randomization code and to output the output data to the data input/output circuit. | 04-17-2014 |
20140119140 | DUTY CYCLE CORRECTOR AND SYSTEMS INCLUDING THE SAME - A duty cycle corrector includes a sensing unit, a pad unit, a fuse unit, and a driver unit. The sensing unit generates at least one sensing signal based on the sensed duty cycle ratio of an output signal. The pad unit outputs at least one decision signal based on the at least one sensing signal. The fuse unit generates a duty cycle control signal based on at least one received fuse control signal. The driver unit adjusts a duty cycle ratio of an input signal to generate the output signal based on the duty cycle control signal. The driver unit adjusts the duty cycle ratio of the input signal by adjusting a pull-up strength or a pull-down strength of the input signal based on the duty cycle control signal. | 05-01-2014 |
20140219036 | EQUALIZER AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - Provided are an equalizer and a semiconductor memory device including the same. The equalizer includes a delay circuit and an inverting circuit. The delay circuit is configured to output, in response to a select signal, one of a delay signal delaying an input signal applied to an input/output node and an inverted signal inverting the input signal. The inverting circuit is configured to invert a signal provided from the delay circuit and output the inverted signal to the input/output node. The equalizer is configured such that when the delay circuit outputs the delay signal, the equalizer operates as an inductive bias circuit amplifying the input signal and outputting the amplified input signal, and when the delay circuit outputs the inverted signal, the equalizer operates as a latch circuit storing and outputting the input signal. | 08-07-2014 |
20140266299 | CIRCUIT AND METHOD FOR ON-DIE TERMINATION, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - An on-die termination (ODT) circuit includes a calibration unit, an offset-code generating unit, an adder, and an ODT unit. The calibration unit generates a pull-up code and a pull-down code. The offset-code generates a pull-up offset code and a pull-down offset code based on a mode-register-set signal, the pull-up code, and the pull-down code. The adder adds the pull-up offset code and the pull-down offset code to the pull-up code and the pull-down code, respectively, and generates a pull-up calibration code and a pull-down calibration code. The ODT unit changes ODT resistance in response to the pull-up calibration code and the pull-down calibration code. | 09-18-2014 |
20150063008 | INPUT DATA ALIGNMENT CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - An input data alignment circuit includes a data sampler, a frequency divider, a polarity determination block, and a data alignment block. The data sampler provides a data sequence based on data serially input according to a data strobe signal. The frequency divider generates a data alignment signal based on a divided frequency of the data strobe signal. The polarity determination block determines a polarity of the data alignment signal and provides a control signal based on the determined polarity. The data alignment block aligns the data sequence in parallel according to data alignment signal and control signal and generates output data. | 03-05-2015 |