| Patent application number | Description | Published |
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| 20080244339 | Read level control apparatuses and methods - Various read level control apparatuses and methods are provided. In various embodiments, the read level control apparatuses may include an error control code (ECC) decoding unit for ECC decoding data read from a storage unit, and a monitoring unit for monitoring a bit error rate (BER) based on the ECC decoded data and the read data. The apparatus may additionally include an error determination unit for determining an error rate of the read data based on the monitored BER, and a level control unit for controlling a read level of the storage unit based on the error rate. | 10-02-2008 |
| 20080273405 | Multi-bit programming device and method of multi-bit programming - A multi-bit programming device and method for a non-volatile memory are provided. In one example embodiment, a multi-bit programming device may include a multi-bit programming unit configured to multi-bit program original multi-bit data to a target memory cell in a memory cell array, and a backup programming unit configured to select backup memory cells in the memory cell array with respect to each bit of the original multi-bit data, and program each bit of the original multi-bit data to a respective one of the selected backup memory cells. | 11-06-2008 |
| 20080276150 | ERROR CONTROL CODE APPARATUSES AND METHODS OF USING THE SAME - An Error Control Code (ECC) apparatus applied to a memory of a Multi-Level Cell (MLC) method may include: a bypass control signal generator generating a bypass control signal; and an ECC performing unit that may include at least two ECC decoding blocks, determining whether to bypass a portion of the at least two ECC decoding blocks based on the bypass control signal, and/or performing an ECC decoding. In addition or in the alternative, the ECC performing unit may include at least two ECC encoding blocks, determining whether to bypass a portion of the at least two ECC encoding blocks based on the bypass control signal, and/or performing an ECC encoding. An ECC method applied to a memory of a MLC method and a computer-readable recording medium storing a program for implementing an EEC method applied to a memory of a MLC method are also disclose. | 11-06-2008 |
| 20080285340 | Apparatus for reading data and method using the same - Disclosed are an apparatus and a method for reading data. The method for reading data according to example embodiments includes comparing a threshold voltage of a memory cell with a first boundary voltage, comparing the threshold voltage with a second boundary voltage having a higher voltage level than that of the first boundary voltage, and determining data of the memory cell based on the threshold voltage, the first boundary voltage, and the second boundary voltage. | 11-20-2008 |
| 20080288849 | Apparatus for generating soft decision values and method thereof - According to an example embodiment, a method of generating a soft decision value using an Analog-to-Digital Converter (ADC) having a given resolution may include receiving metric values calculated based on levels of a transmission signal and output levels of the ADC. Metric values corresponding to a level of a received signal may be selected from among the received metric values. A first maximum metric value may be detected from among the selected metric values when a transmission bit is a first level, and a second maximum metric value may be detected from among the selected metric values when the transmission bit is a second level. The soft decision value may be generated based on a difference between the first maximum metric value and the second maximum metric value. | 11-20-2008 |
| 20080310234 | NONVOLATILE MEMORY DEVICE AND METHODS OF PROGRAMMING AND READING THE SAME - A read method of a non-volatile memory device includes reading an initial threshold voltage value of an index cell from threshold voltage information cells that store information indicating the initial threshold voltage, determining a current threshold voltage value from the index cell, and comparing the initial threshold voltage value and the current threshold voltage value to calculate a shifted threshold voltage level of the index cell. A read voltage is changed by the shifted threshold voltage level to read user data using the changed read voltage. | 12-18-2008 |
| 20090040822 | FLASH MEMORY DEVICE HAVING SINGLE PAGE BUFFER STRUCTURE AND RELATED PROGRAMMING OPERATIONS - A flash memory device is provided, and the flash memory device comprises memory cells, a sense node connected to a selected bit line, a load circuit connected to the sense node, and first and second sense and register circuits, each connected to the sense node. The first sense and register circuit is configured to store a first data value in accordance with the voltage level of the sense node during an initial read interval of a multi-bit program operation. The load circuit is configured to selectively pre-charge the sense node in accordance with the data value stored in the first sense and register circuit during a verify read interval of the multi-bit program operation. A multi-bit programming method for the flash memory device is also provided. | 02-12-2009 |
| 20090067237 | MULTI-BIT DATA MEMORY SYSTEM AND READ OPERATION - Provided is a read operation for a N-bit data non-volatile memory system. The method includes determining in relation to data states of adjacent memory cells associated with a selected memory cell in the plurality of memory cells whether read data obtained from the selected memory cell requires compensation, and if the read data requires compensation, replacing the read data with compensated read data. | 03-12-2009 |
| 20090164710 | SEMICONDUCTOR MEMORY SYSTEM AND ACCESS METHOD THEREOF - A semiconductor memory system and access method thereof. The semiconductor memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory stores monitoring data in one or more of plural memory cells. The memory controller controls the nonvolatile memory. The memory controller detects the monitoring data and adjusts a bias voltage, which is provided to the plural memory cells, in accordance with a result of the detection. | 06-25-2009 |
| 20090196097 | Device for reading memory data and method using the same - Provided are a device for reading memory data and a method using the same. The device for reading memory data comprises a memory cell which stores multi-bit information, an information detection unit which detects as much bit information as a predetermined number of bits from among multi-bit information, a source-line voltage control unit which controls a source-line voltage of the memory cell based on the detected bit information from the information detection unit, and a remaining bit information read unit which reads remaining bit information stored in the memory cell by using the controlled source-line voltage. | 08-06-2009 |
| 20110003458 | METHOD OF FORMING DEVICE ISOLATION LAYER AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - Provided are a method of forming a device isolation layer and a method of fabricating a semiconductor device. The method includes: forming a first trench and a second trench in a substrate, wherein the second trench is connected to the first trench and has a width smaller than the first trench; forming a liner insulation layer in the second trench such that the liner insulation layer is buried in the second trench; and forming a gap fill insulation layer on the liner insulation layer such that the gap fill insulation layer is buried in the first trench. | 01-06-2011 |
| 20110047323 | MEMORY SYSTEM, MULTI-BIT FLASH MEMORY DEVICE, AND ASSOCIATED METHODS - A memory system includes a multi-bit flash memory device and a flash controller configured to control the multi-bit flash memory device. The flash controller is configured to output a series of commands, pointers, and addresses to the multi-bit flash memory device for read/program operations. | 02-24-2011 |
| 20110075484 | NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY SYSTEM EMPLOYING SAME - A nonvolatile memory device comprises a memory cell array, a row selection circuit and a voltage generator. The memory cell array comprises a first dummy memory cell, a second dummy memory cell, and a NAND string comprising a plurality of memory cells coupled in series between a string selection transistor and a ground selection transistor through the first dummy memory cell and the second dummy memory cell. During a read-out operation mode, a dummy read-out voltage is applied to a first dummy wordline coupled to the first dummy memory cell, and to a second dummy wordline coupled to the second dummy memory cell. The dummy read-out voltage has a lower magnitude than a read-out voltage applied to an unselected memory cell during the read-out operation mode. | 03-31-2011 |
| 20110145663 | Read level control apparatuses and methods - Various read level control apparatuses and methods are provided. In various embodiments, the read level control apparatuses may include an error control code (ECC) decoding unit for ECC decoding data read from a storage unit, and a monitoring unit for monitoring a bit error rate (BER) based on the ECC decoded data and the read data. The apparatus may additionally include an error determination unit for determining an error rate of the read data based on the monitored BER, and a level control unit for controlling a read level of the storage unit based on the error rate. | 06-16-2011 |
