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Seung-Beom
Seung Beom Cho, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090291402 | FLAME STRUCTURE OF GAS BURNER - A fire hole part structure of a gas burner, which is constructed to be manufactured at a low cost, can improve flame stability, and can prevent incomplete combustion due to the length of flame. The structure is provided to a premixing ignition burner, which is installed to apply heat to a heat exchanger of a boiler, and includes fire hole pieces which are installed parallel to one another in mounting openings of a burner body, and each of which is defined with fire holes at regular intervals. An upper wall of at least one of the fire hole pieces is bent or curved to extend in at least two directions, and the fire holes are defined through respective surface portions of the upper wall, which extend in different directions, to face different directions. | 11-26-2009 |
Seung Beom Kim, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20100241985 | Providing Virtual Keyboard - Apparatus and methods are described for providing a virtual keyboard. In one aspect, an apparatus for providing a virtual keyboard to be displayed on a touch screen is described. The apparatus includes a memory unit that includes a data repository to store data comprising at least one virtual keyboard configuration information to configure at least one corresponding virtual keyboard. The apparatus includes a processing module to select from the data stored in the data repository a given virtual keyboard configuration information to select a corresponding virtual keyboard to configure; configure the selected virtual keyboard to have a fan-like shape with multiple keys of the virtual keyboard arranged along an outline of an arc in a fan-shaped region based on the selected virtual keyboard configuration information; and instruct a touch screen module to display the configured virtual keyboard on a display region of a touch screen. | 09-23-2010 |
Seung Beom Ryu, Seoul KR
Seung Beom Seo, Yongin KR
| Patent application number | Description | Published |
|---|---|---|
| 20100181588 | SEMICONDUCTOR LIGHT EMITTING DEVICE - Disclosed is a semiconductor light emitting device. The semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and an active layer disposed therebetween, and a surface plasmon layer disposed between the active layer and at least one of the n-type and p-type semiconductor layers, including metallic particles and an insulating material, and including a conductive via for electrical connection between the active layer and the at least one of the n-type and p-type semiconductor layers, wherein the metallic particles are enclosed by the insulating material to be insulated from the at least one of the n-type and p-type semiconductor layers. The semiconductor light emitting device can achieve enhanced emission efficiency by using surface plasmon resonance. Using the semiconductor light emitting device, the diffusion of a metal employed for surface plasmon resonance into the active layer can be minimized. | 07-22-2010 |
Seung-Beom Ahn, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20100094445 | METHOD FOR DESIGNING GLASS ANTENNA - The present invention features a technique comprising the design of a glass antenna having a desired performance regardless of the kind of vehicle and the glass size and the shape of vehicle, by operating an EM (engineering model) simulation tool with an optimization algorithm. | 04-15-2010 |
Seung-Beom Cho, Yuseong-Gu KR
| Patent application number | Description | Published |
|---|---|---|
| 20080236050 | Cerium oxide powder, method for preparing the same, and CMP slurry comprising the same - Disclosed is cerium oxide powder for a CMP abrasive, which can improve polishing selectivity of a silicon oxide layer to a silicon nitride layer and/or within-wafer non-uniformity (WIWNU) during chemical mechanical polishing in a semiconductor fabricating process. More particularly, the cerium oxide powder is obtained by using cerium carbonate having a hexagonal crystal structure as a precursor. Also, CMP slurry comprising the cerium oxide powder as an abrasive, and a shallow trench isolation method for a semiconductor device using the CMP slurry as polishing slurry are disclosed. | 10-02-2008 |
| 20110070737 | METHOD FOR PREPARING OF CERIUM OXIDE POWDER FOR CHEMICAL MECHANICAL POLISHING AND METHOD FOR PREPARING OF CHEMICAL MECHANICAL POLISHING SLURRY USING THE SAME - The present invention relates to a method of preparing a cerium oxide powder for a CMP slurry and a method of preparing a CMP slurry using the same, and more particularly, to a method of preparing a cerium oxide powder for a CMP slurry and a method of preparing a CMP slurry using the same in which the specific surface area of the powder is increased by preparing a cerium precursor, and then decomposing and calcinating the prepared cerium precursor. The pore distribution is controlled to increase the chemical contact area between a polished film and a polishing material, thereby reducing polishing time while the physical strength of powder is decreased, which remarkably reduces scratches on a polished film. | 03-24-2011 |
Seung-Beom Seo, Suwon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090033224 | Plasma display panel and method of manufacturing the same - A plasma display panel and a method of manufacturing the plasma display panel are provided. The plasma display panel includes: a plurality of substrates including a first substrate and a second substrate disposed to face the first substrate; a plurality of barrier ribs disposed between the first substrate and the second substrate and defining a plurality of discharge spaces; a plurality of discharge electrodes disposed between the first substrate and the second substrate; phosphor layers formed in the discharge spaces; and an external light shield layer formed inside the substrates. | 02-05-2009 |
Seung-Beom Yoon, Suwon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20080315289 | ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY (EEPROM) DEVICE AND METHODS OF FABRICATING THE SAME - An EEPROM device includes a device isolation layer disposed at a predetermined region of a semiconductor substrate to define active regions, a pair of control gates crossing the device isolation layers and an active region, a pair of selection gates interposed between the control gates to cross the device isolation layers and the active region and a floating gate and an intergate dielectric pattern stacked sequentially between the control gates and the active region The EEPROM device further includes a gate insulation layer of a memory transistor interposed between the floating gate and the active region and a tunnel insulation layer thinner than the gate insulation layer of the memory transistor and a gate insulation layer of a selection transistor interposed between the selection gates and the active region. The tunnel insulation layer is aligned at one side adjacent to the floating gate. | 12-25-2008 |
| 20080318406 | SPLIT GATE TYPE NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - In a split gate type nonvolatile memory device and a method of fabricating the same. A supplementary layer pattern is disposed on a source region of a semiconductor substrate. Since the source region is vertically extended by virtue of the presence of the supplementary layer pattern, it is therefore possible to increase an area of a region where a floating gate overlaps the source region and the supplementary layer pattern. Accordingly, the capacitance of a capacitor formed between the source and the floating gate increases so that it is possible for the nonvolatile memory device to perform program/erase operations at a low voltage level. | 12-25-2008 |
| 20090011589 | METHOD OF MANUFACTURING SPLIT GATE TYPE NONVOLATILE MEMORY DEVICE - A method of manufacturing a split gate type nonvolatile semiconductor memory device in which control gates are formed by a self aligning process. | 01-08-2009 |
| 20090141562 | NON-VOLATILE MEMORY DEVICE, METHODS OF FABRICATING AND OPERATING THE SAME - A non-volatile memory device includes a floating gate formed on a substrate with a gate insulation layer interposed therebetween, a tunnel insulation layer formed on the floating gate, a select gate electrode inducing charge introduction through the gate insulation layer, and a control gate electrode inducing charge tunneling occurring through the tunnel insulation layer. The select gate electrode is insulated from the control gate electrode. According to the non-volatile memory device, a select gate electrode and a control gate electrode are formed on a floating gate, and thus a voltage is applied to the respective gate electrodes to write and erase data. | 06-04-2009 |
| 20100289071 | NON-VOLATILE MEMORY DEVICE, METHODS OF FABRICATING AND OPERATING THE SAME - A non-volatile memory device includes a floating gate formed on a substrate with a gate insulation layer interposed therebetween, a tunnel insulation layer formed on the floating gate, a select gate electrode inducing charge introduction through the gate insulation layer, and a control gate electrode inducing charge tunneling occurring through the tunnel insulation layer. The select gate electrode is insulated from the control gate electrode. According to the non-volatile memory device, a select gate electrode and a control gate electrode are formed on a floating gate, and thus a voltage is applied to the respective gate electrodes to write and erase data. | 11-18-2010 |