Patent application number | Description | Published |
20090073540 | SEMI-TRANSPARENT/TRANSFLECTIVE LIGHTED INTERFEROMETRIC DEVICES - In certain embodiments, a device is provided that utilizes both interferometrically reflected light and transmitted light. Light incident on the device is interferometrically reflected from a plurality of layers of the device to emit light in a first direction, the interferometrically reflected light having a first color. Light from a light source is transmitted through the plurality of layers of the device to emit from the device in the first direction, the transmitted light having a second color. | 03-19-2009 |
20090080058 | Devices and methods for enhancing color shift of interferometric modulators - The color reflected by an interferometric modulator may vary as a function of the angle of view. A range of colors are thus viewable by rotating the interferometric modulator relative to an observer. By placing a textured layer between an observer and an interferometric modulator, a pattern which includes the range of colors may be viewed by the observer, and the range of colors may thus be viewable from a single viewing angle. | 03-26-2009 |
20100177533 | LARGE AREA LIGHT PANEL AND SCREEN - Embodiments of a panel lighting apparatus and methods of its manufacture are described. In one embodiment, the apparatus can include a light source, an at least partially transparent panel comprising a planar front surface and a planar back surface, the panel disposed in conjunction with the light source such that light from the light source is input into at least one edge of the panel and guided therein, and a plurality of light extraction dots disposed on the planar back surface, the plurality of light extraction dots configured to reflect light incident on the planar back surface and extract light from the light source propagating in the panel through the planar front surface. | 07-15-2010 |
20100187422 | INTEGRATED LIGHT EMITTING AND LIGHT DETECTING DEVICE - Methods and systems for providing a light device that can emit light and sense light are disclosed. In one embodiment, a lighting device includes a light guide having a planar first surface, the light guide configured such that at least some ambient light enters the light guide through the first surface and propagates therein, and at least one light detector disposed along an edge of the light guide, the at least one detector optically coupled to the light guide to receive light propagating therein. The light detector can be configured to produce a control signal. In some embodiments, the lighting device also includes at least one light turning feature disposed on the first surface, the at least one light turning feature configured to direct light incident into the light guide through the first surface. | 07-29-2010 |
20110026095 | DEVICES AND METHODS FOR ENHANCING COLOR SHIFT OF INTERFEROMETRIC MODULATORS - The color reflected by an interferometric modulator may vary as a function of the angle of view. A range of colors are thus viewable by rotating the interferometric modulator relative to an observer. By placing a textured layer between an observer and an interferometric modulator, a pattern which includes the range of colors may be viewed by the observer, and the range of colors may thus be viewable from a single viewing angle. | 02-03-2011 |
20110069371 | SEMI-TRANSPARENT/TRANSFLECTIVE LIGHTED INTERFEROMETRIC DEVICES - In certain embodiments, a device is provided that utilizes both interferometrically reflected light and transmitted light. Light incident on the device is interferometrically reflected from a plurality of layers of the device to emit light in a first direction, the interferometrically reflected light having a first color. Light from a light source is transmitted through the plurality of layers of the device to emit from the device in the first direction, the transmitted light having a second color. | 03-24-2011 |
20120092749 | DEVICES AND METHODS FOR ENHANCING COLOR SHIFT OF INTERFEROMETRIC MODULATORS - The color reflected by an interferometric modulator may vary as a function of the angle of view. A range of colors are thus viewable by rotating the interferometric modulator relative to an observer. By placing a textured layer between an observer and an interferometric modulator, a pattern which includes the range of colors may be viewed by the observer, and the range of colors may thus be viewable from a single viewing angle. | 04-19-2012 |
20120161009 | INTEGRATED LIGHT EMITTING AND LIGHT DETECTING DEVICE - Methods and systems for providing a light device that can emit light and sense light are disclosed. In one embodiment, a lighting device includes a light guide having a planar first surface, the light guide configured such that at least some ambient light enters the light guide through the first surface and propagates therein, and at least one light detector disposed along an edge of the light guide, the at least one detector optically coupled to the light guide to receive light propagating therein. The light detector can be configured to produce a control signal. In some embodiments, the lighting device also includes at least one light turning feature disposed on the first surface, the at least one light turning feature configured to direct light incident into the light guide through the first surface. | 06-28-2012 |
20120217881 | ILLUMINATION SYSTEMS WITH NATURAL AND ARTIFICIAL LIGHT INPUTS - This disclosure provides systems, methods, and apparatus for illumination systems with natural and artificial light inputs. In one aspect, an apparatus can include a natural light collection system, an artificial light collection system, an illumination panel, and a control system. The illumination panel can be optically coupled to the natural light collection system and the artificial light collection system to receive natural and artificial light. The control system can be coupled to the artificial light system and can be configured to control the artificial light system. | 08-30-2012 |
20120230053 | LARGE AREA LIGHT PANEL AND SCREEN - Embodiments of a panel lighting apparatus and methods of its manufacture are described. In one embodiment, the apparatus can include a light source, an at least partially transparent panel comprising a planar front surface and a planar back surface, the panel disposed in conjunction with the light source such that light from the light source is input into at least one edge of the panel and guided therein, and a plurality of light extraction dots disposed on the planar back surface, the plurality of light extraction dots configured to reflect light incident on the planar back surface and extract light from the light source propagating in the panel through the planar front surface. | 09-13-2012 |
20120230054 | LARGE AREA LIGHT PANEL AND SCREEN - Embodiments of a panel lighting apparatus and methods of its manufacture are described. In one embodiment, the apparatus can include a light source, an at least partially transparent panel comprising a planar front surface and a planar back surface, the panel disposed in conjunction with the light source such that light from the light source is input into at least one edge of the panel and guided therein, and a plurality of light extraction dots disposed on the planar back surface, the plurality of light extraction dots configured to reflect light incident on the planar back surface and extract light from the light source propagating in the panel through the planar front surface. | 09-13-2012 |
20130249293 | FUNCTIONAL BACK GLASS FOR A SOLAR PANEL - A photovoltaic solar panel includes a front glass, a back glass, and a photovoltaic (PV) power generating layer encapsulated between the front glass and the back glass. The PV power generating layer is configured to convert ambient electromagnetic energy, received through the front glass, to a direct current (DC) power output. The PV solar panel also includes at least one component, disposed behind the PV power generating layer, selected from the group consisting of: a direct current to alternating current (DC-AC) inverter configured to convert the DC power output from the PV power generator to an alternating current (AC) power output, a battery, and an antenna. | 09-26-2013 |
Patent application number | Description | Published |
20120143861 | PREDICTIVE CONVERSION SYSTEMS AND METHODS - In one embodiment, a system and method of predicting sale transaction conversion rate of an item operates through a search of information in response to a query over a network. The system and method can includes discovering available information of the item of interest, extracting certain of the available information of the item, analyzing the certain information by comparing the information to other item information, weighting the information for the item in comparison to other items of the category, calculating a predictive score for the item of interest, and presenting the information of the item of interest ranked according to the predictive score as compared to other items of the category. | 06-07-2012 |
20120143924 | PREDICTIVE CONVERSION SYSTEMS AND METHODS - In one embodiment, a system and method of predicting sale transaction conversion rate of an item operates through a search of information in response to a query over a network. The item can be included in a category of items. Information for other relevant items of the category is available through network query and historical data, among others. Respective information for the other items of the category is available to the method. The system and method includes discovering available information of the item of interest, extracting certain of the available information of the item, analyzing the certain information for the item by comparing the information to other item information for the category of items, weighting the information for the commercial item in comparison to other items of the category, calculating a predictive score for the commercial item of interest, and presenting the information of the commercial item of interest ranked according to the predictive score as compared to other items of the category. | 06-07-2012 |
20130282734 | PREDICTIVE CONVERSION SYSTEMS AND METHODS - In one embodiment, a system and method of predicting sale transaction conversion rate of an item operates through a search of information in response to a query over a network. The item can be included in a category of items. Information for other relevant items of the category is available through network query and historical data, among others. Respective information for the other items of the category is available to the method. The system and method includes discovering available information of the item of interest, extracting certain of the available information of the item, analyzing the certain information for the item by comparing the information to other item information for the category of items, weighting the information for the commercial item in comparison to other items of the category, calculating a predictive score for the commercial item of interest, and presenting the information of the commercial item of interest ranked according to the predictive score as compared to other items of the category. | 10-24-2013 |
20150220876 | PREDICTIVE CONVERSION SYSTEMS AND METHODS - In one embodiment, a system and method of predicting sale transaction conversion rate of an item operates through a search of information in response to a query over a network. The item can be included in a category of items. Information for other relevant items of the category is available through network query and historical data, among others. Respective information for the other items of the category is available to the method. The system and method includes discovering available information of the item of interest, extracting certain of the available information of the item, analyzing the certain information for the item by comparing the information to other item information for the category of items, weighting the information for the commercial item in comparison to other items of the category, calculating a predictive score for the commercial item of interest, and presenting the information of the commercial item of interest ranked according to the predictive score as compared to other items of the category. | 08-06-2015 |
Patent application number | Description | Published |
20080215822 | PCI Express Enhancements and Extensions - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 09-04-2008 |
20100174872 | Media Memory System - A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors. | 07-08-2010 |
20110072164 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 03-24-2011 |
20110072234 | Providing Hardware Support For Shared Virtual Memory Between Local And Remote Physical Memory - In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed. | 03-24-2011 |
20110154079 | Instruction For Enabling A Procesor Wait State - In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed. | 06-23-2011 |
20110161703 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 06-30-2011 |
20110173367 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 07-14-2011 |
20110208925 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 08-25-2011 |
20110238882 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 09-29-2011 |
20110314480 | Apparatus, System, And Method For Persistent User-Level Thread - Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof. | 12-22-2011 |
20120017221 | Mechanism for Monitoring Instruction Set Based Thread Execution on a Plurality of Instruction Sequencers - A technique to monitor software thread performance and update software that issues or uses the thread(s) to reduce performance-inhibiting events. At least one embodiment of the invention uses hardware and/or software timers or counters to monitor various events associated with executing user-level threads and report these events back to a user-level software program, which can use the information to avoid or at least reduce performance-inhibiting events associated with the user-level threads. | 01-19-2012 |
20120036293 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 02-09-2012 |
20120089750 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 04-12-2012 |
20120254563 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 10-04-2012 |
20130054940 | MECHANISM FOR INSTRUCTION SET BASED THREAD EXECUTION ON A PLURALITY OF INSTRUCTION SEQUENCERS - In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed. | 02-28-2013 |
20130091317 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 04-11-2013 |
20130097353 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 04-18-2013 |
20130111086 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS | 05-02-2013 |
20130132622 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus forenhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 05-23-2013 |
20130132636 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 05-23-2013 |
20130132683 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus forenhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 05-23-2013 |
20130185580 | INSTRUCTION FOR ENABLING A PROCESOR WAIT STATE - In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed. | 07-18-2013 |
20130219399 | MECHANISM FOR INSTRUCTION SET BASED THREAD EXECUTION OF A PLURALITY OF INSTRUCTION SEQUENCERS - In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed. | 08-22-2013 |
20130246824 | Instruction For Enabling A Processor Wait State - In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed. | 09-19-2013 |
20130275735 | Apparatus, System, And Method For Persistent User-Level Thread - Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof. | 10-17-2013 |
20140075129 | SYSTEMS AND METHODS EXCHANGING DATA BETWEEN PROCESSORS THROUGH CONCURRENT SHARED MEMORY - A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors. | 03-13-2014 |
20140115594 | MECHANISM TO SCHEDULE THREADS ON OS-SEQUESTERED SEQUENCERS WITHOUT OPERATING SYSTEM INTERVENTION - Method, apparatus and system embodiments to schedule OS-independent “shreds” without intervention of an operating system. For at least one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. A scheduler routine may run on each enabled sequencer. The schedulers may retrieve shred descriptors from a queue system. The sequencer associated with the scheduler may then execute the shred described by the descriptor. Other embodiments are also described and claimed. | 04-24-2014 |
20140208042 | PROVIDING HARDWARE SUPPORT FOR SHARED VIRTUAL MEMORY BETWEEN LOCAL AND REMOTE PHYSICAL MEMORY - In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed. | 07-24-2014 |
20150149683 | PCI EXPRESS TRANSACTION DESCRIPTOR - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 05-28-2015 |
20150161050 | PCI EXPRESS PREFETCHING - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 06-11-2015 |
Patent application number | Description | Published |
20140303980 | SYSTEM AND METHOD FOR AUDIO KYMOGRAPHIC DIAGNOSTICS - A system and method for assisting in a determination of one or more maladies associated with a human voice anatomy utilizes voice information acquired over at least two temporally displaced acquisitions. Acquired voice samples, including plural vowel sounds, are digitized and passed through one or more bandpass filters to isolate one or more frequency ranges. Curve fitting of acquired data is completed in accordance with a plurality of parameter weights applied in either a time domain or frequency domain model of the voice. This process is repeated a second, later time, for the same human, and the same process is completed for the subsequently-acquired voice information. A difference between the curve information in the respective data sets is analyzed relative to the weights, and corresponding changes are correlated to maladies of various areas of the human voice anatomy. | 10-09-2014 |
20140323875 | STENT APPARATUS WITH INTEGRATED IMAGING ELEMENT FOR IN SITU DETECTION OF BUILDUP OF MATERIAL IN A VASCULAR SYSTEM - According to one embodiment, an apparatus for detecting obstructions in biological vessels includes a cylindrical hollow stent with an expandable body portion having an outer surface configured to engage the inner surface of the lumen of the vessel to urge the vessel against collapse, and an imaging system operatively coupled with stent. The imaging system includes a first power source, a light generating element, a light sensor generating a first signal representative of light received by the sensor element from the light generating elements, and a processor unit receiving the first signal and processing the first signal in accordance with image processing logic stored in a memory of the processor unit to generate an image signal representative of as image of associated target material such as plaque obstructing the flow. The imaging system and stent may be formed on opposite sides of a flexible organic substrate. | 10-30-2014 |
20140347512 | IMAGING SENSOR AND METHOD FOR BIOMETRIC MAPPING OF FACIAL SKIN - A diagnostic system for biometric mapping of facial skin includes a light filter a light sensor, a non-transient memory, a correlation processor, and an output unit. The light filter filters light reflected from an object to a filtered light signal. The light sensor receives the filtered light signal and generates a first electronic image signal representative of an image of the object in accordance with the filtered light signal. The memory stores a first electronic diagnostic signal representative of a predetermined mal-condition of the object. The processor determines a correlation between the first electronic image signal and the first electronic diagnostic signal, generates a correlation signal representative of a strength of the correlation, determines a diagnosis of the associated object based on the correlation signal, and generates a diagnosis signal in accordance with the diagnosis. The output unit generates a diagnosis result signal in accordance with the diagnosis signal. | 11-27-2014 |
20140356966 | METHOD AND APPARATUS FOR DETECTION OF BIOLOGICAL CONDITIONS - A system and method for analysis of fluids, particularly bodily fluids such as saliva, uses an active, electrically-driven substrate for supporting an amalgamate of fluid and nanoparticles selected to adhere to one or more proteins. The nanoparticles affect light that is directed on or through the amalgamate. Different light directions, light polarization planes, and light wavelengths are used to obtain optical properties of the amalgamate. Once obtained, these values are compared to earlier or baseline values to determine a property of the amalgamate. Values or ranges are compared to earlier values, suitably with empirical association with maladies or conditions, to facilitate detection or diagnosis. | 12-04-2014 |
20140359304 | TRUSTED MANAGER BRIDGE - A system and method for securing processing devices includes a police bridge disposed in one or more data busses between a central processing and input/output peripherals, components or components. The police bridge is suitably disposed between northbridge logic and southbridge logic. Alternatively, or in addition to such placement, a police bridge is suitably place between southbridge logic and super I/O logic. A police bridge is suitably a system-on-chip or fixed or programmable hardware. The police bridge monitors or controls its associated bus to determine whether acceptable data, with an associated certificate in other embodiments, is being communicated and signaling is generated accordingly. | 12-04-2014 |
20150103591 | SEMICONDUCTOR MEMORY WITH INTEGRATED BIOLOGIC ELEMENT - A memory includes cytokines, such as macromolecule proteins, as a poly-state data storage. Each fold state of multiple fold states of a protein are associated with a data value. Current flow through the protein is associated with a resistance of the protein associated with its current fold state. Application of light, electric fields or heat via an associated element or elements facilitates placement of a protein in a fold state that corresponds to an associated resistance and correlates with an incoming data value. Measuring of current or resistance allows for reading of a data value associated with the protein. | 04-16-2015 |