Patent application number | Description | Published |
20140117354 | SEMICONDUCTOR PACKAGE - A semiconductor package including a first semiconductor package including a first terminal and a second terminal provided on a surface different from a surface on which the first terminal is formed, and a second semiconductor package including a third terminal connected to the first terminal, wherein the surface on which the first terminal is formed faces a surface on which the third terminal is formed. | 05-01-2014 |
20140117430 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a first substrate, a plurality of memory chips horizontally disposed on the first substrate, and having one surfaces which face the first substrate, other surfaces which face away from the one surfaces, and first bumps formed on the other surfaces, a second substrate disposed on the plurality of memory chips and electrically connected, a sub-substrate horizontally disposed on the first substrate together with the plurality of memory chips and electrically connecting the first substrate and the second substrate, and a driving chip having second bumps on one surface thereof and mounted to the second substrate such that the second bumps are electrically connected with the second substrate. | 05-01-2014 |
20140124921 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate; a driving chip having first bumps on a first surface and bump pads on a second surface facing away from the first surface, and mounted to the substrate by the medium of the first bumps; a support member disposed on the substrate substantially horizontally with respect to the driving chip; and a plurality of memory chips substantially horizontally disposed on the driving chip and the support member such that one corner portions of the memory chips are positioned on the driving chip while being centered about the driving chip, wherein the respective memory chips have second bumps which are electrically connected with the respective bump pads of the driving chip, on one surfaces of the one corner portions of the memory chips which face the driving chip. | 05-08-2014 |
20140167280 | SEMICONDUCTOR DEVICE - A semiconductor device including a chip stack structure having a plurality of semiconductor chips, the semiconductor chips being stacked such that they are electrically connected using through-electrodes, and a support frame attached to a side surface of the chip stack structure. | 06-19-2014 |
20140241079 | CHIP DIE AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A chip die including a first input/output (I/O) pad configured to transmit/receive an I/O signal of a memory cell array included in the chip die; a second I/O pad configured to, if a stacked chip die exists on the chip die, transmit/receive a via I/O signal of the stacked chip die, and configured to, if the stacked chip die does not exist on the chip die, transmit/receive a differential I/O signal of the chip die; and an I/O driver configured to receive an operation mode signal including information as to whether the stacked chip die exists on the chip die in such a manner that the second I/O pad is configured to transmit/receive the via I/O signal or the differential I/O signal. | 08-28-2014 |
20140285253 | STACK PACKAGE - A stack package may include a plurality of chips stacked with a plurality of layers; and a chip selection controller configured to provide a reference and chip selection control signal to the plurality of chips. Each chip may comprise: a reference signal controller configured to transmit the reference signal through a first line interconnecting the plurality of chips; a chip selection delay unit configured to control a delay timing point of the chip selection control signal to transmit the control result to each node of a second line interconnecting the plurality of chips; a delay-time-difference sensing unit configured to calculate a delay time difference between a signal applied to each node of the first and second line to generate chip selection information corresponding to the calculated delay time difference; and a memory unit configured to store the chip selection information. | 09-25-2014 |
20140328104 | SEMICONDUCTOR DEVICE - A logic chip and memory chip stacked over the logic chip, the logic chip having a first surface facing the memory chip and a second surface opposite to the first surface and including: first and second internal input/output circuit units for exchanging signals; first external input/output circuit unit for exchanging signals through first external input/output pads formed according to an external interface standard of a first memory over the second surface; and second external input/output circuit unit for exchanging signals through second external input/output pads formed according to an external interface standard of a second memory over the second surface, wherein semiconductor device operates in one of a first mode in which the first internal input/output circuit unit and the first external input/output circuit unit are enabled and a second mode in which the first and second internal input/output circuit units and the second external input/output circuit unit are enabled. | 11-06-2014 |
20150048957 | DATA INPUT/OUTPUT DEVICE AND SYSTEM INCLUDING THE SAME - A data input/output (I/O) device includes a plurality of data units and an I/O assembly. The plurality of data units is coupled to a global I/O (GIO) line through corresponding local I/O (LIO) lines and configured to receive or transmit a plurality of data groups through the corresponding LIO lines. At least one of the plurality of data units have a different operation speed. The I/O assembly performs serial/parallel conversion operations on the plurality of data groups including a high-speed data group and outputs results of the serial/parallel conversion operations. The high-speed data group is output from the at least one of the plurality of data units having the different operation speed. | 02-19-2015 |