Patent application number | Description | Published |
20090003090 | Impedance adjusting circuit and semiconductor memory device having the same - An impedance adjusting circuit includes: a calibration circuit configured to generate a first calibration code and a second calibration code for determining termination resistance; a transmission line circuit configured to transfer the first calibration code during a first section and to transfer the second calibration code during a second section; and a termination resistor circuit adapted to match an impedance with a resistance determined by receiving the first and second calibration codes. | 01-01-2009 |
20090052260 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device having read and write operations includes a discrimination signal generating unit for generating a discrimination signal during the write operation; and a selective delay unit for receiving and selectively delaying a command-group signal in response to the discrimination signal. | 02-26-2009 |
20090059681 | SEMICONDUCTOR MEMORY DEVICE - Semiconductor memory device includes a detection circuit configured to detect a voltage level of an external power supply voltage and a core voltage generation circuit configured to vary a voltage level of the core voltage according to an output signal of the detection circuit to generate a uniform core voltage. | 03-05-2009 |
20090115480 | Clock control circuit and data alignment circuit including the same - A clock control circuit can prevent a malfunction that occurs when a rising strobe signal and a falling strobe signal change in pulse width and thus overlap each other. The clock control circuit which includes a first clock control unit configured to receive a rising strobe signal and a falling strobe signal and output an adjusted rising strobe signal, an enable pulse width of which does not overlap an enable pulse width of the falling strobe signal. | 05-07-2009 |
20090172479 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR TESTING THE SAME - A semiconductor memory device includes an alignment unit configured to align data received from the outside, a plurality of data input/output lines corresponding to the aligned data, respectively and a realignment unit configured to change correspondence between the data and the data input/output lines in response to one or more change signals in a test mode. A method for testing the semiconductor memory device includes inputting data in series using a testing apparatus, aligning the serial data in parallel, and realigning the parallel data in response to one or more change signals. | 07-02-2009 |
20090273364 | CALIBRATION CIRCUIT, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND OPERATING METHOD OF THE CALIBRATION CIRCUIT - Calibration circuit, semiconductor memory device including the same, and operation method of the calibration circuit includes a calibration unit configured to generate a calibration code for controlling a termination resistance value, a calibration control unit configured to count a clock and allow the calibration unit to be enabled during a predetermined clock and a clock control unit configured to selectively supply the clock to the calibration control unit according to an operation mode of a semiconductor device employing the calibration circuit. | 11-05-2009 |
20100329050 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device having read and write operations includes a discrimination signal generating unit for generating a discrimination signal during the write operation; and a selective delay unit for receiving and selectively delaying a command-group signal in response to the discrimination signal. | 12-30-2010 |
20110234288 | INTERNAL VOLTAGE GENERATING CIRCUIT FOR PREVENTING VOLTAGE DROP OF INTERNAL VOLTAGE - An internal voltage generating circuit is utilized to perform a TDBI (Test During Burn-in) operation for a semiconductor device. The internal voltage generating circuit produces an internal voltage at a high voltage level, as an internal voltage, in not only a standby section but also in an active section in response to a test operation signal activated in a test operation. Accordingly, dropping of the internal voltage in the standby section of the test operation and failure due to open or short circuiting are prevented. As a result, reliability of the semiconductor chip, by preventing the generation of latch-up caused by breakdown of internal circuits, is assured. | 09-29-2011 |
20120044773 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device having read and write operations includes a discrimination signal generating unit for generating a discrimination signal during the write operation and a selective delay unit for receiving and selectively delaying a command-group signal in response to the discrimination signal. | 02-23-2012 |
Patent application number | Description | Published |
20090086552 | SEMICONDUCTOR MEMORY DEVICE AND ITS DRIVING METHOD - A semiconductor memory device including a first latch that latches a Mode Register Set (MRS) code consisting of multiple bits in response to an MRS command pulse, a code controller that generates a control signal in response to a code value of preset bits out of an output signal from the first latch, a second latch that selectively latches the output signal from the first latch in response to the control signal and a mode decoder that decodes an output signal from the second latch to output an operation mode. | 04-02-2009 |
20090185439 | ARCHITECTURE OF HIGHLY INTEGRATED SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a first row control circuit region corresponding to a first memory bank; a first column control circuit region corresponding to the first memory bank; a second row control circuit region corresponding to a second memory bank and disposed adjacent to the first row control circuit region; and a second column control circuit region corresponding to a third memory bank and disposed adjacent to the first column control circuit region. | 07-23-2009 |
20090322387 | OUTPUT ENABLE SIGNAL GENERATION CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE - A circuit for generating an output enable signal includes a reset signal generator for synchronizing a reset signal with an external clock signal to generate an output enable (OE) reset signal, synchronizers for synchronizing the OE reset signal with an internal clock signal to generate a source reset signal, and an output enable signal output unit, reset by the source reset signal, for counting pulses of the external clock signal and the internal clock signal to output an output enable signal corresponding to a read command and CAS latency. | 12-31-2009 |
20090323451 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device that prevents a power noise generated at a data input/output pad in a read operation from affecting a data strobe signal pad. The semiconductor memory device includes first power supply voltage pads for a data output circuit, a first power mesh, and a second power supply voltage pad for a data strobe signal output circuit. The first power mesh connects first power supply voltage pads to one another. The second power supply voltage pad is electrically separated from the first power mesh. | 12-31-2009 |
20120200329 | SEMICONDUCTOR DEVICE - A semiconductor device includes a package substrate having a plurality of external connection terminals disposed on a first surface thereof and a plurality of internal connection terminals disposed on a second surface thereof and electrically connected with corresponding one of the external connection terminals, a first semiconductor chip stacked over the second surface of the package substrate and having a first flag pad for providing first information and a first internal circuit for adjusting a parameter by a first correction value in response to the first information provided from the first flag pad, and a second semiconductor chip stacked over the first semiconductor chip and having a second flag pad for providing second information and a second internal circuit for adjusting the parameter by a second correction value in response to the second information provided from the second flag pad. | 08-09-2012 |
20130111101 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF | 05-02-2013 |
20150085563 | MEMORY AND MEMORY SYSTEM INCLUDING THE SAME - A memory includes a plurality of word lines each coupled to one or more memory cells, an address storage unit suitable for storing an address of a word line selected for access by a control unit among the plurality of word lines at a first time point; and the control unit suitable for sequentially refreshing the plurality of word lines in response to application of a refresh command, refreshing one or more adjacent word lines adjacent to a word line corresponding to the address stored in the address storage unit in response to every Nth application of the refresh command where N is a natural number and selecting one or more of the plurality of word lines for access, wherein the first time point is included in time section other than a refresh section in which the control unit refreshes one or more word lines in response to application of the refresh command. | 03-26-2015 |
20150085564 | MEMORY AND MEMORY SYSTEM INCLUDING THE SAME - A memory includes a plurality of word lines each coupled to one or more memory cells, an address storage unit suitable for storing an address of a word line selected for access by a control unit among the plurality of word lines at a first time point; and the control unit suitable for sequentially refreshing the plurality of word lines in response to application of a refresh command, refreshing one or more adjacent word lines adjacent to a word line corresponding to the address stored in the address storage unit in response to every Nth application of the refresh command where N is a natural number and selecting one or more of the plurality of word lines for access, wherein the first time point is included in time section other than a refresh section in which the control unit refreshes one or more word lines in response to application of the refresh command. | 03-26-2015 |