Patent application number | Description | Published |
20090046177 | Method and apparatus for canceling fixed pattern noise in CMOS image sensor - An apparatus for canceling a fixed pattern noise in a CMOS image sensor includes a storage device, a fixed pattern noise operation circuit, and a fixed pattern noise canceling circuit. The storage device stores first reference fixed pattern noises operated in a vertical blank section of an (n−1)th frame. The fixed pattern noise operation circuit calculates second reference fixed pattern noises based on the first reference fixed pattern noises stored in the storage device and blank fixed pattern noises output in a vertical blank section of an n-th frame and outputs the second reference fixed pattern noises to the storage device to update the first reference fixed pattern noises to the second reference fixed pattern noises. The fixed pattern noise canceling circuit cancels active fixed pattern noises in combination signals based on the combination signals output in an active section of an (n+1)th frame and including the active fixed pattern noises and pixel signals and the second reference fixed pattern noises output from the storage device. | 02-19-2009 |
20090261998 | APPARATUS AND METHOD FOR SIGMA-DELTA ANALOG TO DIGITAL CONVERSION - A method and apparatus are provided for sigma-delta (ΣΔ) analog to digital conversion, the method including receiving an analog signal, sampling the received signal, comparing the sampled signal with a constant reference voltage, providing at least one high-order bit responsive to the constant reference comparison, comparing the sampled signal with a variable reference voltage, providing at least one low-order bit responsive to the variable reference comparison, and combining the at least one high-order bit with the at least one low-order bit; and the apparatus including a comparator, a first ADC portion supplying the comparator with a constant reference voltage for providing at least one high-order bit, and a second ADC portion supplying the comparator with a variable reference voltage for providing at least One low-order bit. | 10-22-2009 |
20090289823 | Sigma-delta analog-to-digital converter and solid-state image pickup device - A sigma-delta analog-to-digital converter may include a sigma-delta modulator and a decimation filter. The sigma-delta modulator may convert a first analog input signal into a first bit stream having a first pattern using sigma-delta modulation and convert a second analog input signal into a second bit stream having a second pattern using the sigma-delta modulation. The decimation filter may integrate the number of bits having a particular value in the first bit stream, output a first digital value, calculate a bitwise complement value of the first digital value, integrate the number of bits having the particular value in the second bit stream with the bitwise complement value of the first digital value as an initial value of a second digital value, and output the second digital value. | 11-26-2009 |
20090295956 | Decimation filters, analog-to-digital converters including the same, and image sensors including the converters - An image sensor includes an analog-to-digital converter (ADC) and a decimation filter. The decimation filter includes a first digital data generator and a second digital data generator. The first digital data generator is configured to integrate sigma-delta modulated M-bit pixel data and output N-bit pixel data based on an integration result. The second digital data generator is configured to integrate the N-bit pixel data, generate P-bit pixel data based on an integration result, and output the P-bit pixel data as decimated data. | 12-03-2009 |
20100110256 | Pixel sensor array and image sensor including the same - Provided are a pixel sensor array and a complementary metal-oxide semiconductor (CMOS) image sensor including the same. The pixel sensor array includes a photoelectric transformation element configured to generate electric charges in response to incident light. A signal transmitting circuit is configured to output the electric charges accumulated in the photoelectric transformation element to a first node based on a first control signal, change an electric potential of the first node to an electric potential of a second signal line based on a second control signal, and output a signal sensed in the first node to a first signal line based on a third control signal. A switch element is configured to connect a supply power terminal to the second signal line based on a fourth control signal. A comparator connected to the first signal line and the second signal line and configured to compare a voltage of the signal and a voltage of a reference signal. | 05-06-2010 |
20100171644 | Analog digital converters and image sensors including the same - The analog-digital converter (ADC) includes a modulator and a digital integrator. The modulator is configured to modulate an input signal and output a modulated signal. The digital integrator includes a plurality of accumulators serially connected to one another. The digital integrator is configured to integrate the modulated signal to output an integration result. | 07-08-2010 |
20100177220 | Image sensor for reducing kick-back noise and image pick-up device having the same - An image sensor comprises a plurality of pixel units connected to a column line, a signal process circuit configured to process a signal output from the column line according to a switching operation, and a kick-back noise blocking circuit configured to reduce kick-back noise caused by the switching operation. Each of the pixel units includes a photoelectric conversion element. The kick-back noise blocking circuit is connected between the column line and the signal process circuit. | 07-15-2010 |
20100208114 | Two-path sigma-delta analog-to-digital converter and image sensor including the same - A two-path sigma-delta analog-to-digital converter and an image sensor including the same are provided. The two-path sigma-delta analog-to-digital converter includes at least one integrator configured to integrate a first integrator input signal during a second half cycle of a clock signal and integrate a second integrator input signal during a first half cycle of the clock signal by using a single operational amplifier; a quantizer configured to quantize integrated signals from the at least one integrator and output a first digital signal and a second digital signal; and a feedback loop configured to feed back the first and second digital signals to an input of the at least one integrator. A first analog signal and a second analog signal respectively input from two input paths are respectively converted to the first and second digital signals using the single operational amplifier, thereby increasing power efficiency and reducing an area. | 08-19-2010 |
20100225794 | Digital filter, analog-to-digital converter, and applications thereof - In one embodiment, the ADC includes a modulator configured to generate a symbol sequence, an operand generator configured to generate operands, and a selector configured to selectively output at least one of (1) a reference value and (2) at least one of the operands based on the symbol sequence. The ADC further includes an accumulator configured to accumulate output from the selector. | 09-09-2010 |
20100265114 | Analog-to-digital conversion and implementations thereof - In one embodiment, an analog-to-digital converter (ADC) includes a comparator and a supply circuit. The comparator is configured to compare an input signal to a reference signal. The supply circuit is configured to supply the reference signal. The supply circuit is configured to provide different circuit configurations for supplying the reference signal during different stages of analog-to-digital conversion such that the reference signal is scaled in substantially a same manner during at least two of the stages. | 10-21-2010 |
20110043676 | CMOS IMAGE SENSOR AND IMAGE SIGNAL DETECTING METHOD - A CMOS image sensor includes a photodiode, a switch configured to transfer a signal sensed by the photodiode to a sensing node, and a comparator electrically and directly connected to the sensing node and configured to compare the sensed signal of the sensing node and a ramp signal. Reset offset of the comparator is maintained at a constant offset voltage level during an initialization mode. | 02-24-2011 |
20110050473 | Analog-to-digital converters, and image sensors and image processing devices having the same - An analog-digital converter (ADC) includes a correlated double sampling (CDS) circuit configured to perform CDS on each of a reset signal and an image signal output from a pixel to generate a correlated double sampled reset signal and a correlated double sampled image signal, respectively. A delta sigma (ΔΣ) ADC, also included in the ADC, is configured to output a difference between a first digital code that is generated by performing ΔΣ analog-digital conversion on the correlated double sampled reset signal and a second digital code that is generated by performing ΔΣ analog-digital conversion on the correlated double sampled image signal. | 03-03-2011 |
20110069191 | Correlated double sampling circuit, image sensor including the same, and image processing system including the image sensor - A correlated double sampling (CDS) circuit is provided. The CDS circuit is configured to perform a CDS on a reset signal and an image signal during a CDS phase respectively. The CDS circuit includes a sampling circuit configured to output a difference between a correlated double sampled reset signal and a correlated double sampled image signal, and a feedback unit configured to feedback the difference output from the sampling circuit during a PGA phase to an input of the sampling circuit. | 03-24-2011 |
20110069211 | ANALOG-TO-DIGITAL CONVERTER FOR CONTROLLING GAIN BY CHANGING A SYSTEM PARAMETER, IMAGE SENSOR INCLUDING THE ANALOG-TO-DIGITAL CONVERTER AND METHOD OF OPERATING THE ANALOG-TO-DIGITAL CONVERTER - Example embodiments are directed to an analog-to-digital converter (ADC) that controls a gain by changing a system parameter, an image sensor including the ADC and a method of operating the ADC. The ADC includes a sigma-delta modulator which receives an input signal and a clock signal and sigma-delta modulates the input signal into a digital output signal based on the clock signal and an accumulation unit which accumulates the digital output signal at each cycle of the clock signal according to an analog-to-digital conversion time and outputs an accumulation result. A system parameter is varied during the analog-to-digital conversion time to control a gain of the ADC. The method of operating the analog-to-digital converter includes sigma-delta modulating an input signal into a digital output signal in response to a clock signal input to the ADC; and accumulating the digital output signal at each cycle of the input clock signal according to an analog-to-digital conversion time and outputting an accumulation result. | 03-24-2011 |
20110266417 | DIGITAL DOUBLE SAMPLING METHOD, A RELATED CMOS IMAGE SENSOR, AND A DIGITAL CAMERA COMPRISING THE CMOS IMAGE SENSOR - A digital double sampling method, a related complementary metal oxide semiconductor (CMOS) image sensor, and a digital camera comprising the CMOS image sensor are disclosed. The method includes generating first digital data corresponding to an initial voltage level apparent in a pixel in response to a reset signal, inverting the first digital data, outputting a detection voltage corresponding to image data received from outside of the CMOS image sensor, and counting in synchronization with a clock signal, starting from an initial value equal to the inverted first digital data, and for an amount of time responsive to a voltage level of the detection voltage. | 11-03-2011 |
20110279718 | AMPLIFIER FOR REDUCING HORIZONTAL BAND NOISE AND DEVICES HAVING THE SAME - An amplifier is provided. The amplifier includes a differential amplifier including a tail, a current mirror connected between output terminals of the differential amplifier and a power line receiving a supply voltage, and a first switching circuit for connecting and disconnecting one of the output terminals of the differential amplifier to and from the tail in response to a first switching signal. | 11-17-2011 |
20120002093 | CORRELATED DOUBLE SAMPLING CIRCUIT AND IMAGE SENSOR INCLUDING THE SAME - A correlated double sampling circuit includes a delta-sigma modulator, a selection circuit, and an accumulation circuit. The delta-sigma modulator is configured to receive an input signal, delta-sigma modulate the input signal, and output a modulation signal. The selection circuit is configured to invert the modulation signal and selectively output one of the modulation signal and an inverted modulation signal in response to a selection signal corresponding to an operation phase. The accumulation circuit is configured to generate a first accumulation result by performing an accumulation process on one of the modulation signal and the inverted modulation signal in a first operation phase, and generate a second accumulation result by performing the accumulation process on the first accumulation result and the other one of the modulation signal and the inverted modulation signal in a second operation phase. | 01-05-2012 |
20120097840 | ANALOG-TO-DIGITAL CONVERTER AND IMAGE SENSOR INCLUDING SAME - An analog-to-digital converter (ADC) within an image sensor includes a comparator comparing a ramp signal with an image signal, and a counter generating a count result in response to the comparison by counting a clock during a counting interval. The ADC determines whether a first counting interval for the counter is less than a reference interval, and if the first counting interval is less than the reference interval the counting interval is a first counting interval, else the counting interval is a second counting interval. | 04-26-2012 |
20120133808 | CORRELATED DOUBLE SAMPLING CIRCUIT, METHOD THEREOF AND DEVICES HAVING THE SAME - A CDS circuit is provided. The CDS circuit includes a signal compressor which compresses each of a pixel signal and a ramp signal using capacitive dividing and outputs a compressed pixel signal and a compressed ramp signal, and a comparator which compares the compressed pixel signal with the compressed ramp signal and outputs a comparative signal corresponding to a comparison result. | 05-31-2012 |
20120138775 | DATA SAMPLER, DATA SAMPLING METHOD, AND PHOTO DETECTING APPARATUS INCLUDING DATA SAMPLER - A data sampler and a photo detecting apparatus compensate a reference signal with offset information measured from a unit pixel, and compare an offset-compensated reference signal with a data signal, thereby minimizing the impact of an offset occurring with an increase of gain in the data sampler. | 06-07-2012 |
20120140089 | IMAGE SENSOR AND CAMERA SYSTEM HAVING THE SAME - An image sensor includes a reference voltage generation unit that generates a reference voltage that alternately decreases and increases at a constant rate in an operation mode of the image sensor to convert analog signals of detected incident light to a digital value using the reference voltage to determine an intensity of the incident light with high sensitivity and high signal-to-noise ratio. | 06-07-2012 |
20130134520 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a semiconductor device including a high voltage transistor and a low voltage transistor and a method of manufacturing the same. The semiconductor device includes a semiconductor substrate including a high voltage region and a low voltage region; a high voltage transistor formed in the high voltage region and including a first active region, a first source/drain region, a first gate insulating layer, and a first gate electrode; and a low voltage transistor formed in the low voltage region and including a second active region, a second source/drain region, a second gate insulating layer, and a second gate electrode. The second source/drain region has a smaller thickness than a thickness of the first source/drain region. | 05-30-2013 |
20130162857 | IMAGE SENSORS AND IMAGE PROCESSING SYSTEMS - An image sensor includes a delta-sigma analog-to-digital converter (ADC) including a delta-sigma modulator (DSM) and a voltage adjusting circuit. The DSM is configured to perform delta-sigma modulation on an analog signal from a unit pixel. The delta-sigma ADC is configured to convert the analog signal to a digital signal. The voltage adjusting circuit includes a replica inverter having a same configuration as at least one inverter included in the DSM. The voltage adjusting circuit is configured to adjust a power supply voltage and an input voltage provided to the at least one inverter based on a current flowing in the replica inverter. | 06-27-2013 |
20130215307 | CDS CIRCUIT, IMAGE SENSOR INCLUDING THE SAME, AND IMAGE PROCESSING DEVICE INCLUDING THE IMAGE SENSOR - A correlated double sampling (CDS) circuit includes a correction circuit configured to receive an input pixel signal through a first node via a column line, correct the input pixel signal, and output the corrected pixel signal through a second node; and a comparator including first and second input terminals, the first input terminal being connected to the second node and being configured to receive the corrected pixel signal, and the second input terminal configured to receive a ramp signal, the comparator being configured to compare the corrected pixel signal with the ramp signal and output a comparison signal indicating a result of the comparing, wherein the correction circuit includes, a first capacitor connected between the first and second nodes, and one or more metal lines disposed adjacent to the first capacitor, and wherein at least one other capacitor is formed by the first capacitor and the metal line. | 08-22-2013 |
20130270420 | CORRELATED DOUBLE SAMPLING CIRCUIT AND IMAGE SENSOR INCLUDING THE SAME - A correlated double sampling (CDS) circuit included in an image sensor includes a sampling unit and a timing controlled band-limitation (TCBL) unit. The sampling unit is configured to generate an output signal by performing a CDS operation with respect to a reset component of an input signal and an image component of the input signal based on a ramp signal, the input signal being provided from a pixel array included in the image sensor. The TCBL unit is connected to the sampling unit, and is configured to remove noise from the output signal based on a timing control signal. The timing control signal is activated during a first comparison duration, in which a first comparison operation is performed with respect to the ramp signal and the reset component of the input signal, and during a second comparison duration, in which a second comparison operation is performed with respect to the ramp signal and the image component of the input signal. | 10-17-2013 |
20130321694 | IMAGE SYSTEMS AND SENSORS HAVING FOCUS DETECTION PIXELS THEREIN - Image sensors include an array of image sensor pixels therein. This array of image sensor pixels includes a first focus detection pixel and at least a first color pixel. A switching network is provided, which is electrically coupled to the array. This switching network may be configured to generate a first mixed image signal by electronically mixing a focus detection signal generated by the first focus detection pixel with at least one color pixel signal generated by the at least a first color pixel. The first focus detection pixel can be a color-blind pixel, which may include a light-blocking shield mask therein. | 12-05-2013 |
20140014815 | RAMP SIGNAL GENERATOR FOR CMOS IMAGE SENSOR - A ramp signal generator includes: a row decoder which receives a row control signal from a timing controller and generates one or more row select signals, a first column decoder which receives a first column control signal from the timing controller and generates one or more first column select signals, a second column decoder which receives a second column control signal from the timing controller and generates one or more second column select signals, and a current cell array which is activated by the one or more first column select signals, the one or more second column select signals, and the one or more row select signals, and includes at least one current cell which generates at least one unit current, and generates an output current by summing the generated at least one unit current. | 01-16-2014 |
20140070974 | ANALOG-TO-DIGITAL CONVERSION CIRCUIT, AND IMAGE SENSOR INCLUDING THE SAME - One embodiment of an analog-to-digital converter includes at least one comparator and a restriction circuit. The comparator has first and second input nodes and a connection node. The connection node is one of an internal node and an output node of the comparator. The restriction circuit is electrically connected to the connection node, and the restriction circuit is configured to restrict a voltage of the connection node. | 03-13-2014 |
20140145067 | IMAGE SENSOR AND SYSTEM INCLUDING THE SAME - An image sensor includes a first column pair and a second column pair among a plurality of columns of a pixel array, an analog-to-digital converter pair, and a switch arrangement circuit configured to connect the first column pair with the analog-to-digital converter pair in response to first switch control signals such that two rows among a plurality of rows in the pixel array are read during a single access time. | 05-29-2014 |
20140204250 | IMAGE SENSOR, OPERATING METHOD THEREOF, AND SYSTEM INCLUDING SAME - A method of operating an image processing system includes storing differences between first analog pixel signals and second analog pixel signals and converting the stored differences to one-bit digital signals, the first analog pixel signals being output from a plurality of pixels and corresponding to a previous frame, and the second analog pixel signals being output from the plurality of pixels and corresponding to a current frame. | 07-24-2014 |
20140232890 | IMAGE SENSOR AND COMPUTING SYSTEM HAVING THE SAME - An image sensor includes a pixel array and an analog-to-digital (A/D) conversion unit. The pixel array generates an analog signal by sensing an incident light. The A/D conversion unit generates a digital signal in a first operation mode by performing a sigma-delta A/D conversion and a cyclic A/D conversion with respect to the analog signal and generates the digital signal in a second operation mode by performing a single-slope A/D conversion with respect to the analog signal. The image sensor provides a high-quality image in a still image photography mode and a dynamic image video mode. | 08-21-2014 |
20140267861 | IMAGE SENSORS - An image sensor includes a pixel array and a plurality of pairs of column lines. The pixel array includes a plurality of unit pixel areas arranged in a plurality of rows and columns. Each of the unit pixel areas includes a readout circuit connected to a corresponding pair of column lines, and first and second photo-electric conversion devices sharing the readout circuit. Each of the unit pixel areas is configured to output a first pixel signal corresponding to a photoelectron generated by the first photo-electric conversion device through the first column line, and to output a second pixel signal corresponding to a photoelectron generated by the second photo-electric conversion device through the second column line. | 09-18-2014 |
20140293106 | ANALOG-TO-DIGITAL CONVERSION CIRCUIT, AND IMAGE SENSOR INCLUDING THE SAME - One embodiment of an analog-to-digital converter includes at least one comparator and a restriction circuit. The comparator has first and second input nodes and a connection node. The connection node is one of an internal node and an output node of the comparator. The restriction circuit is electrically connected to the connection node, and the restriction circuit is configured to restrict a voltage of the connection node. | 10-02-2014 |
20140333813 | CORRELATED DOUBLE SAMPLING CIRCUIT, METHOD THEREOF AND DEVICES HAVING THE SAME - A CDS circuit includes first capacitors; second capacitors; and a switch arrangement which, in response to a switch control signal, connects the first capacitors in series between a pixel signal output node and a ground to compress the pixel signal and connects the second capacitors in series between a ramp signal output node and the ground to compress the ramp signal, or connects the first capacitors in parallel between the pixel signal output node and a first input node of the comparator and connects the second capacitors in parallel between the ramp signal output node and a second input node of the comparator. | 11-13-2014 |
20140357035 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a semiconductor device including a high voltage transistor and a low voltage transistor and a method of manufacturing the same. The semiconductor device includes a semiconductor substrate including a high voltage region and a low voltage region; a high voltage transistor formed in the high voltage region and including a first active region, a first source/drain region, a first gate insulating layer, and a first gate electrode; and a low voltage transistor formed in the low voltage region and including a second active region, a second source/drain region, a second gate insulating layer, and a second gate electrode. The second source/drain region has a smaller thickness than a thickness of the first source/drain region. | 12-04-2014 |
20140368706 | PROGRAMMABLE GAIN AMPLIFIER AND DEVICES INCLUDING THE SAME - A programmable gain amplifier includes a sampling circuit, a source follower, a first capacitor and an error amplifier. The sampling circuit is configured to perform correlated double sampling on an input signal using a reference voltage. The first capacitor is connected between the sampling circuit and the source follower. The error amplifier is connected between an input terminal of the source follower and an output terminal of the source follower. The error amplifier is configured to reset a voltage of the output terminal of the source follower to the reference voltage during a source follower reset operation. | 12-18-2014 |
20150022702 | ANALOG-TO-DIGITAL CONVERTER, IMAGE SENSOR INCLUDING THE SAME, AND IMAGE PROCESSING DEVICE INCLUDING THE IMAGE SENSOR - An analog-to-digital converter includes a gain amplification unit configured to receive a pixel signal at a first node and to amplify a gain of the pixel signal, a first capacitor connected between the first node and a second node, an amplifier configured to receive and amplify a signal output from the gain amplification unit and the first capacitor, and a conversion circuit configured to convert an output signal of the amplifier to a digital signal based on a reference signal and output the digital signal as a first output signal. | 01-22-2015 |
20150029355 | IMAGE SENSORS AND IMAGING DEVICES INCLUDING THE SAME - A pixel array includes pixels arranged in a grid, with separate readout paths configured to readout image data from different subsets of the pixels in the array. An image sensor may employ image data from one subset of pixels, which may include fewer pixels than another subset of pixels in the array, to quickly form an image. | 01-29-2015 |