Patent application number | Description | Published |
20100083066 | SYSTEM AND METHOD FOR AUTOMATIC COMMUNICATION LANE FAILOVER IN A SERIAL LINK - A system for automatic lane failover includes a first device coupled to a second device via a serial communication link having a plurality of a communication lanes. The devices may communicate by operating the link in a normal mode and a degraded mode. During normal mode operation, the devices may send frames of information to each other via the serial communication link. Each frame of information may include a number of data bits and a number of error protection bits. In response to either device detecting a failure of one or more of the communication lanes, the first device may cause the serial communication link to operate in a degraded mode by removing the one or more failed communication lanes. In addition, each device may reformat and send the frame of information on the remaining communication lanes with fewer data bits and the same number of error protection bits. | 04-01-2010 |
20100211742 | CONVEYING CRITICAL DATA IN A MULTIPROCESSOR SYSTEM - A system for conveying critical and non-critical words of multiple cache lines includes a first node interface of a first processing node receiving, from a first processor, a first request identifying a critical word of a first cache line and a second request identifying a critical word of a second cache line. The first node interface conveys requests corresponding to the first and second requests to a second node interface of a second processing node. The second node interface receives the corresponding requests and conveys the critical words of the first and second cache lines to the first processing node before conveying non-critical words of the first and second cache lines. | 08-19-2010 |
20120081157 | POWER-SUPPLY NOISE SUPPRESSION USING A FREQUENCY-LOCKED LOOP - An integrated circuit that includes a digitally controlled oscillator (DCO) that adjusts a clock frequency of a critical path of the integrated circuit based on the variations in a power-supply voltage of the DCO and the critical path is described. This DCO may be included in a feedback control loop that includes a frequency-locked loop (FLL), and which determines an average clock frequency of the critical path based on a reference frequency. Furthermore, the DCO may have a selectable delay characteristic that specifies a delay sensitivity of the DCO as a function of the power-supply voltage, thereby approximately matching a manufactured delay characteristic of the critical path. Additionally, for variations in the power-supply voltage having frequencies greater than a resonance frequency associated with a chip package of the integrated circuit, adjustments of the clock frequency may be proportional to the variations in the power-supply voltage and the selectable delay characteristic. | 04-05-2012 |
20120218034 | VOLTAGE CALIBRATION METHOD AND APPARATUS - A method and apparatus for power supply calibration to reduce voltage guardbands is disclosed. In one embodiment, an integrated circuit (IC) includes a voltage measurement unit configured to measure an operating voltage during a start-up procedure. The IC further includes a comparator configured to compare the measured operating voltage to a target voltage. The comparator is further configured to cause a change to a supply voltage (upon which the operating voltage is based) if the operating voltage is not within a target voltage range and to repeat the measurement of the operating voltage. If the operating voltage is within the target voltage range, the comparator is configured to inhibit further changes to the operating voltage. | 08-30-2012 |
20130311814 | CONSTANT FREQUENCY ARCHITECTURAL TIMER IN A DYNAMIC CLOCK DOMAIN - Implementations of the present disclosure involve an apparatus and/or method for providing a constant frequency timer signal for a microprocessor that operates with varying core clock signals. The apparatus and/or method utilizes a code generator, such as a gray code generator, operating on a reference clock signal that allows the constant frequency timer signal to be either faster or slower than the core clock frequency. More particularly, the apparatus and/or method may compute a difference between previous gray code samples and add the calculated difference to a software visible reference clock signal such that constant frequency timer signal may be faster or slower than the core clock signal. Through the use of the apparatus and/or method, a core clock signal may be reduced as needed to provide operational power savings to the microprocessor and the computing system employing the techniques described herein, while maintaining synchronization between the executing programs of the computing system. | 11-21-2013 |
20140040526 | COHERENT DATA FORWARDING WHEN LINK CONGESTION OCCURS IN A MULTI-NODE COHERENT SYSTEM - Systems and methods for efficient data transport across multiple processors when link utilization is congested. In a multi-node system, each of the nodes measures a congestion level for each of the one or more links connected to it. A source node indicates when each of one or more links to a destination node is congested or each non-congested link is unable to send a particular packet type. In response, the source node sets an indication that it is a candidate for seeking a data forwarding path to send a packet of the particular packet type to the destination node. The source node uses measured congestion levels received from other nodes to search for one or more intermediate nodes. An intermediate node in a data forwarding path has non-congested links for data transport. The source node reroutes data to the destination node through the data forwarding path. | 02-06-2014 |
20140095909 | MULTIPLE CLOCK DOMAIN CYCLE SKIPPING UTILIZING OPTIMAL MASKS TO MINIMIZE VOLTAGE NOISE - Implementations of the present disclosure involve an apparatus and/or method for providing one or more clock signals that include a skipped clock cycle to a portion of a computing system. The skipped cycle clock signals may be changed by the computing system during operation of the system by altering masks applied to a global clock signal. However, the flexibility to alter various skipped cycle clock signals may introduce noise or signal disruptions within the system. Thus, the present disclosure may also involve an apparatus and/or method for managing the altering of the clock cycle skipping masks to manage the voltage noise introduced into the system by the adjustment of the operating frequency of the portions of the system. In one embodiment, the method includes prioritizing or otherwise ordering the bits of the masks applied to the global clock signal to attempt to prevent similar bits from being altered simultaneously. | 04-03-2014 |
20140354264 | HIGH SPEED CLOCK CYCLE RATE DIGITAL VOLTAGE MONITOR WITH TRIGGERED TRACING FOR INTEGRATED CIRCUITS - Implementations of the present disclosure involve a system and/or method for measuring on-die voltage levels of an integrated circuit through a digital sampling circuit. In particular, the system and/or method utilizes a delay line based analog-to-digital sampling circuit that produces a voltage reading over time, such as at every high frequency clock cycle. The digitized samples are routed to either an on-die memory structure for later analysis or are transmitted to one or more pins of a chip for capture and analysis by an external analyzer. | 12-04-2014 |