Patent application number | Description | Published |
20090243813 | WIRELESS PROGRAMMING OF NON-VOLATILE MEMORY WITH NEAR-FIELD UHF COUPLING - Near-Field UHF wireless coupling may be used to write data into a non-volatile memory in a device, thus allowing for changes to be made to the device after that product has been manufactured. Energy from the received wireless signal may be used to power sufficient circuitry in the device so that the programming does not require an on-board power source such as a battery. In many cases, the device may be programmed after it has been packaged for shipment/sale, without removing the device from the package. In some embodiments, a multi-segment antenna may be used to program multiple such devices at the same time by the same Near-Field UHF signal. | 10-01-2009 |
20100250798 | HIERARCHICAL MEMORY ARCHITECTURE WITH AN INTERFACE TO DIFFERING MEMORY FORMATS - A hierarchical memory storage using a concentrator device that is located between a processor and memory storage devices to provide an interface to accommodate different memory formats. | 09-30-2010 |
20100250819 | HIERARCHICAL MEMORY ARCHITECTURE USING A CONCENTRATOR DEVICE - A hierarchical memory storage using a concentrator device that is located between a processor and memory devices. The concentrator device includes a page buffer, a Phase-Change Memory (PCM) memory array, and a configurable Error-Correcting Code (ECC) engine to accommodate temporary storage for data transfers between the processor and the memory devices. | 09-30-2010 |
20100250843 | HIERARCHICAL MEMORY ARCHITECTURE WITH A PHASE-CHANGE MEMORY (PCM) CONTENT ADDRESSABLE MEMORY (CAM) - A Phase-Change Memory (PCM) Content Addressable Memory (CAM) utilized to store addresses of defective rows or columns of a memory array or memories attached to a backside bus of a concentrator device. | 09-30-2010 |
20100250849 | HIERARCHICAL MEMORY ARCHITECTURE TO CONNECT MASS STORAGE DEVICES - A hierarchical memory storage using a concentrator device that is located between a processor and memory storage devices to provide a succession of memory devices and enable attachment of a memory depth to a processor controller with a limited pin count. | 09-30-2010 |
20100318718 | MEMORY DEVICE FOR A HIERARCHICAL MEMORY ARCHITECTURE - A hierarchical memory device having multiple interfaces with different memory formats includes a Phase Change Memory (PCM). An input port and an output port connect the hierarchical memory device in a daisy-chain hierarchy or a hierarchical tree structure with other memories. Standard non-hierarchical memory devices can also attach to the output port of the hierarchical memory device. | 12-16-2010 |
20110066796 | AUTONOMOUS SUBSYSTEM ARCHITECTURE - An autonomous sub-system receives a database downloaded from a host controller. A controller monitors bus traffic and/or allocated resources in the subsystem and re-allocates resources based on the monitored results to dynamically improve system performance. | 03-17-2011 |
20110067039 | AUTONOMOUS MEMORY ARCHITECTURE - An autonomous memory device in a distributed memory sub-system can receive a database downloaded from a host controller. The autonomous memory device can pass configuration routing information and initiate instructions to disperse portions of the database to neighboring die using an interface that handles inter-die communication. Information is then extracted from the pool of autonomous memory and passed through a host interface to the host controller. | 03-17-2011 |
20120137195 | PRESERVING DATA INTEGRITY IN A MEMORY SYSTEM - A method includes detecting that a first device in a memory array has degraded, the first device storing a portion of a data record, wherein the data record is encoded using a first error control technique. The method continues with recovering the data record using portions of the data record stored in devices other than the first device in the memory array and encoding the data record using a second error control technique. The method also includes storing the data record in the devices of the memory array other than the first device. | 05-31-2012 |
20120198205 | TRANSACTIONAL MEMORY - Subject matter disclosed herein relates to techniques to perform transactions using a memory device. | 08-02-2012 |
20120221917 | ERROR CONTROL IN MEMORY STORAGE SYSTEMS - A method includes calculating a first syndrome of a codeword read from a memory location under a first set of conditions and calculating a second syndrome of the codeword read from the memory location under a second set of conditions. The method also includes analyzing the first and second syndromes and applying one of the first and second syndromes to the codeword to find the codeword having a minimum number of errors. | 08-30-2012 |
20120278554 | HIERARCHICAL MEMORY ARCHITECTURE TO CONNECT MASS STORAGE DEVICES - A hierarchical memory storage using a concentrator device that is located between a processor and memory storage devices to provide a succession of memory devices and enable attachment of a memory depth to a processor controller with a limited pin count. | 11-01-2012 |
20120311393 | APPARATUSES, SYSTEMS, DEVICES, AND METHODS OF REPLACING AT LEAST PARTIALLY NON-FUNCTIONAL PORTIONS OF MEMORY - Subject matter disclosed herein relates to determining that a portion of a memory is at least partially non-functional, replacing the portion of at least partially non-functional memory; and adjusting an error detection and/or correction process responsive to determining that the portion of the memory is at least partially non-functional and/or replacing the portion of at least partially non-functional memory. | 12-06-2012 |
20140047283 | APPARATUSES, SYSTEMS, DEVICES, AND METHODS OF REPLACING AT LEAST PARTIALLY NON-FUNCTIONAL PORTIONS OF MEMORY - Subject matter disclosed herein relates to determining that a portion of a memory is at least partially non-functional, replacing the portion of at least partially non-functional memory; and adjusting an error detection and/or correction process responsive to determining that the portion of the memory is at least partially non-functional and/or replacing the portion of at least partially non-functional memory. | 02-13-2014 |
20140129872 | ERROR CONTROL IN MEMORY STORAGE SYSTEMS - A method includes calculating a first syndrome of a codeword read from a memory location under a first set of conditions and calculating a second syndrome of the codeword read from the memory location under a second set of conditions. The method also includes analyzing the first and second syndromes and applying one of the first and second syndromes to the codeword to find the codeword having a minimum number of errors. | 05-08-2014 |
20140351630 | APPARATUSES, SYSTEMS, DEVICES, AND METHODS OF REPLACING AT LEAST PARTIALLY NON-FUNCTIONAL PORTIONS OF MEMORY - Subject matter disclosed herein relates to determining that a portion of a memory is at least partially non-functional, replacing the portion of at least partially non-functional memory; and adjusting an error detection and/or correction process responsive to determining that the portion of the memory is at least partially non-functional and/or replacing the portion of at least partially non-functional memory. | 11-27-2014 |
20150033087 | RESTING BLOCKS OF MEMORY CELLS IN RESPONSE TO THE BLOCKS BEING DEEMED TO FAIL - In an embodiment, a block of memory cells is rested in response to the block of memory cells being deemed to fail. For some embodiments, a rested block may be selected for use in response to passing an operation. In other embodiments, a rested block may be rested again or may be permanently retired from further use in response to failing the operation. | 01-29-2015 |
20150052114 | METHODS AND SYSTEMS FOR AUTONOMOUS MEMORY SEARCHING - Methods and systems operate to receive a plurality of search requests for searching a database in a memory system. The search requests can be stored in a FIFO queue and searches can be subsequently generated for each search request. The resulting plurality of searches can be executed substantially in parallel on the database. A respective indication is transmitted to a requesting host when either each respective search is complete or each respective search has generated search results. | 02-19-2015 |