Patent application number | Description | Published |
20110115078 | FLIP CHIP PACKAGE - A flip chip package may include a semiconductor chip, a package substrate, a conductive magnetic bump and an anisotropic conductive member. The semiconductor chip may have a first pad. The package substrate may have a second pad confronting the first pad. The conductive magnetic bump may be interposed between the semiconductor chip and the package substrate to generate a magnetic force. The anisotropic conductive member may be arranged between the semiconductor chip and the package substrate. The anisotropic conductive member may have conductive magnetic particles induced toward the conductive magnetic bump by the magnetic force to electrically connect the first pad with the second pad. A predetermined number of the conductive magnetic particles may be positioned between the conductive magnetic bump and the pad, so that an electrical connection reliability between the pads may be increased. | 05-19-2011 |
20120028412 | SEMICONDUCTOR APPARATUS, METHOD OF MANUFACTURING THE SAME, AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - A semiconductor apparatus having a through electrode, a semiconductor package, and a method of manufacturing the semiconductor package are provided. The method of includes preparing a substrate including a buried via, the buried via having a first surface at a first end, and the buried via extending from a first substrate surface of the substrate into the substrate; planarizing a second substrate surface of the substrate opposite the first substrate surface to form a through via by exposing a second via surface at a second end of the buried via opposite the first end; forming a conductive capping layer on the exposed second via surface of the through via; and recessing the second substrate surface so that at least a first portion of the through via extends beyond the second substrate surface. | 02-02-2012 |
20120056330 | SEMICONDUCTOR DEVICE - A semiconductor device may include a substrate and a through electrode. The substrate may have a first surface and a second surface opposite to the first surface, the substrate including circuit patterns formed on the first surface. The through electrode penetrates the substrate and may be electrically connected to the circuit pattern, the through electrode including a first plug that extends from the first surface in a thickness direction of the substrate and a second plug that extends from the second surface in the thickness direction of the substrate so as to be connected to the first plug. | 03-08-2012 |
20120133048 | SEMICONDUCTOR DEVICE, FABRICATING METHOD THEREOF AND SEMICONDUCTOR PACKAGE INCLUDING THE SEMICONDUCTOR DEVICE - In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector. | 05-31-2012 |
20120199981 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a first device including a first substrate and a first external connection terminal for connecting outside the first device; a second device stacked on the first device, the second device including a second substrate and a second external connection terminal for connecting outside the second device; an adhesive pattern disposed between the first device and second device, the adhesive pattern disposed in locations other than locations where the first external connection terminal and second external connection terminal are disposed, and the adhesive pattern causing the first device and second device, when stacked, to be spaced apart by a predetermined distance; and a plated layer disposed between and electrically and physically connecting the first external connection terminal and the second external connection terminal. | 08-09-2012 |
20120326307 | STACKED SEMICONDUCTOR DEVICE - A stacked semiconductor device including a plurality of semiconductor chips stacked vertically, a plurality of scribe lane elements each forming a step with a semiconductor chip of the plurality of semiconductor chips and respectively formed on a side surface of each of the plurality of semiconductor chips, a redistribution element respectively formed on each of the plurality of semiconductor chips and the scribe lane elements, and a signal connection member formed on the side surface of each of the plurality of semiconductor chips and electrically connecting the redistribution elements. | 12-27-2012 |
20140057430 | SEMICONDUCTOR DEVICE, FABRICATING METHOD THEREOF AND SEMICONDUCTOR PACKAGE INCLUDING THE SEMICONDUCTOR DEVICE - In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector. | 02-27-2014 |
20150194366 | HEAT TRANSFER STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention provides a heat transfer structure which includes a first object, a second object and a thermal transfer adhesive material which is placed between the first object and the second object so as to be in contact with at least one of the first object or the second object. The heat transfer adhesive material includes a resin and at least one thermal conductive material, and the at least one thermal conductive material is distributed by being dispersed in the resin and forms surface contact with at least one of the first object or the second object. | 07-09-2015 |