Patent application number | Description | Published |
20090008737 | Image Sensor Having Anti-Reflection Film and Method of Manufacturing the Same - Provided is an image sensor and a method of manufacturing the same. The image sensor includes anti-reflection films which are formed between a plurality of metal wire lines of the lowest metal wiring layer and a semiconductor substrate and between one of the metal wiring layers and another metal wiring layer. | 01-08-2009 |
20100176271 | PIXEL ARRAY PREVENTING THE CROSS TALK BETWEEN UNIT PIXELS AND IMAGE SENSOR USING THE PIXEL - The present invention provides a pixel array having a three-dimensional structure and an image sensor having the pixel array. The pixel array has a three-dimensional structure in which a photodiode, a transfer transistor, a reset transistor, a convert transistor, and a select transistor are divided and formed on a first wafer and a second wafer, chips on the first and second wafers are connected in a vertical direction after die-sorting the chips. The first wafer includes a plurality of photodiodes for generating electric charges corresponding to an incident video signal, a plurality of transfer transistors for transferring the electric charges generated by the photodiodes to floating diffusion regions, a plurality of STIs circling one of the photodiodes and one transfer transistor connected to the one photodiode, a first super-contact which extends from a lower portion of the plurality of the STIs to a lower surface of the wafer, and a second super-contact which penetrates the plurality of the STIs and a portion of the first super-contact. The electric charges accumulated in the floating diffusion regions are transferred to the second wafer through the second super-contact. | 07-15-2010 |
20100264504 | IMAGE SENSOR HAVING WAVE GUIDE AND METHOD FOR MANUFACTURING THE SAME - An image sensor having a wave guide includes a semiconductor substrate formed with a photodiode and a peripheral circuit region; an anti-reflective layer formed on the semiconductor substrate; an insulation layer formed on the anti-reflective layer; a wiring layer formed on the insulation layer and connected to the semiconductor substrate; at least one interlayer dielectric stacked on the wiring layer; and a wave guide connected to the insulation layer by passing through the interlayer dielectric and the wiring layer which are formed over the photodiode. | 10-21-2010 |
20110133176 | Transistor and electronic apparatus including same - Transistors and electronic apparatuses including the same are provided, the transistors include a channel layer on a substrate. The channel layer includes a zinc (Zn)-containing oxide. The transistors include a source and a drain, respectively, contacting opposing ends of the channel layer, a gate corresponding to the channel layer, and a gate insulating layer insulating the channel layer from the gate. The channel layer has a first surface adjacent to the substrate, a second surface facing the first surface, and a channel layer-protection portion on the second surface. The channel layer-protection portion includes a fluoride material. | 06-09-2011 |
20110156113 | BACK SIDE ILLUMINATION IMAGE SENSOR REDUCED IN SIZE AND METHOD FOR MANUFACTURING THE SAME - A back side illumination image sensor reduced in chip size has a capacitor disposed in a vertical upper portion of a pixel region in the back side illumination image sensor in which light is illuminated from a back side of a subscriber, thereby reducing a chip size, and a method for manufacturing the back side illumination image sensor. The capacitor of the back side illumination image sensor reduced in chip size is formed in the vertical upper portion of the pixel region, not in the outside of a pixel region, so that the outside area of the pixel region for forming the capacitor is not required, thereby reducing a chip size. | 06-30-2011 |
20110207258 | METHOD FOR FORMING PAD IN WAFER WITH THREE-DIMENSIONAL STACKING STRUCTURE - A method for forming a pad in a wafer with a three-dimensional stacking structure includes: (a) a first process of bonding a device wafer and a handling wafer; (b) a second process of thinning a back side of an Si substrate which is formed on the device wafer, after the first process; (c) a third process of forming an anti-reflective layer and a PMD (preferential metal deposition) dielectric layer, after the second process; (d) a fourth process of forming vias on back sides of super contacts which are formed on the Si substrate, after the third process; and (e) a fifth process of forming a pad, after the fourth process. | 08-25-2011 |
20120295389 | IMAGE SENSOR HAVING WAVE GUIDE AND METHOD FOR MANUFACTURING THE SAME - An image sensor having a wave guide includes a semiconductor substrate formed with a photodiode and a peripheral circuit region; an anti-reflective layer formed on the semiconductor substrate; an insulation layer formed on the anti-reflective layer; a wiring layer formed on the insulation layer and connected to the semiconductor substrate; at least one interlayer dielectric stacked on the wiring layer; and a wave guide connected to the insulation layer by passing through the interlayer dielectric and the wiring layer which are formed over the photodiode. | 11-22-2012 |
20120301996 | BACK SIDE ILLUMINATION IMAGE SENSOR REDUCED IN SIZE AND METHOD FOR MANUFACTURING THE SAME - A back side illumination image sensor reduced in chip size has a capacitor disposed in a vertical upper portion of a pixel region in the back side illumination image sensor in which light is illuminated from a back side of a subscriber, thereby reducing a chip size, and a method for manufacturing the back side illumination image sensor. The capacitor of the back side illumination image sensor reduced in chip size is formed in the vertical upper portion of the pixel region, not in the outside of a pixel region, so that the outside area of the pixel region for forming the capacitor is not required, thereby reducing a chip size. | 11-29-2012 |
20130189828 | METHOD FOR FORMING PAD IN WAFER WITH THREE-DIMENSIONAL STACKING STRUCTURE - A method for forming a pad in a wafer with a three-dimensional stacking structure includes: (a) a first process of bonding a device wafer and a handling wafer; (b) a second process of thinning a back side of an Si substrate which is formed on the device wafer, after the first process; (c) a third process of forming an anti-reflective layer and a PMD (preferential metal deposition) dielectric layer, after the second process; (d) a fourth process of forming vias on back sides of super contacts which are formed on the Si substrate, after the third process; and (e) a fifth process of forming a pad, after the fourth process. | 07-25-2013 |