Patent application number | Description | Published |
20080206921 | METHODS OF FORMING PHASE CHANGEABLE LAYERS INCLUDING PROTRUDING PORTIONS IN ELECTRODES THEREOF - A method of forming a structure in a phase changeable memory cell can include forming a bottom electrode having an interlayer dielectric layer thereon, the bottom electrode having a recess therein that extends beyond a boundary between the bottom electrode and the interlayer dielectric. A phase changeable layer can be formed in the recess including a protruding potion of the phase changeable layer that protrudes into the bottom electrode beyond the boundary. | 08-28-2008 |
20100315866 | PHASE CHANGE MEMORY DEVICE HAVING MULTI-LEVEL AND METHOD OF DRIVING THE SAME - A phase change memory device having a multi-level and a method of driving the same are presented. The disclosed phase change memory device includes variable resistors and shifting units. The variable resistors are interchanged into set and reset states in response to an applied current. The shifting units, which are connected to the variable resistors, shift resistance distribution in the set and reset state of the variable resistors by a predetermined level. | 12-16-2010 |
20100321989 | FUSION MEMORY DEVICE EMBODIED WITH PHASE CHANGE MEMORY DEVICES HAVING DIFFERENT RESISTANCE DISTRIBUTIONS AND DATA PROCESSING SYSTEM USING THE SAME - A fusion memory device having phase change memory devices that have different resistance distributions and a corresponding data processing system is presented. The fusion memory device includes a first and a second phase change memory group arranged on the same chip. Because the second phase change memory group exhibits a resistance distribution different from that of the first phase change memory group, then the fusion memory device can be configured to simultaneously function as both a DRAM device and as a flash memory device. Because the first and second phase change memory groups can be composed of similar PRAM components, the corresponding manufacturing and driving circuitry is markedly simplified as compared to other fusion memory devices that have dissimilar DRAM and flash memory components. | 12-23-2010 |
20110073829 | PHASE CHANGE MEMORY DEVICE HAVING A HEATER WITH A TEMPERATURE DEPENDENT RESISTIVITY, METHOD OF MANUFACTURING THE SAME, AND CIRCUIT OF THE SAME - A phase change memory device having a heater that exhibits a temperature dependent resistivity which provides a way of reducing a reset current is presented. The phase change memory device includes a phase change pattern and a heating electrode contacted with the phase change pattern. The heating electrode includes a smart heating electrode such that the smart heating layer is formed of a conduction material that exhibits an increase in resistance as a function of an increase in temperature, i.e., a positive temperature dependent resistivity. | 03-31-2011 |
20110075473 | CIRCUIT AND METHOD FOR GENERATING REFERENCE VOLTAGE, PHASE CHANGE RANDOM ACCESS MEMORY APPARATUS AND READ METHOD USING THE SAME - A circuit for generating a reference voltage includes at least one reference cell, a reference cell write driver, a reference cell sense amplifier, and a voltage compensation unit. The reference cell is a variable resistance memory cell. The reference cell write driver writes data to the reference cell. The reference cell sense amplifier reads out the data stored in the reference cell on the basis of a predetermined reference voltage. A voltage compensation unit outputs a compensation reference voltage by controlling the reference voltage in accordance with the output value of the sense amplifier. | 03-31-2011 |
20110121250 | HIGH INTEGRATION PHASE CHANGE MEMORY DEVICE HAVING REDUCED THICKNESS PHASE CHANGE LAYER AND FABRICATION METHOD THEREOF - A high integration phase change memory device includes a semiconductor substrate including an access device, a heating electrode formed on the access device, a phase change nano band formed on the heating electrode, and an interlayer insulating layer for supporting the phase change nano band formed in both sides of the phase change nano band. | 05-26-2011 |
20110188302 | METHOD OF DRIVING PHASE CHANGE MEMORY DEVICE CAPABLE OF REDUCING HEAT DISTURBANCE - A method of driving phase change memory device which reduces or prevents unwanted heat disturbances from interfering with memory states in adjacent memory cells is presented. The phase change memory cells are disposed at word and bit line intersections. The method includes collectively erasing all of the memory cells as a unit in the bit line into a reset state. The method then includes individually programming only selected memory cells of the memory cells into set states. | 08-04-2011 |
20120294073 | METHOD OF DRIVING PHASE CHANGE MEMORY DEVICE CAPABLE OF REDUCING HEAT DISTURBANCE - A method of driving phase change memory device which reduces or prevents unwanted heat disturbances from interfering with memory states in adjacent memory cells is presented. The phase change memory cells are disposed at word and bit line intersections. The method includes collectively erasing all of the memory cells as a unit in the bit line into a reset state. The method then includes individually programming only selected memory cells of the memory cells into set states. | 11-22-2012 |
20120329984 | POLYARYLENE SULFIDE AND PREPARATION METHOD THEREOF - This disclosure relates to polyarylene sulfide that may exhibit and maintain excellent properties and a method for preparing the same, wherein the polyarylene sulfide is in the form of pellet of 2 to 10 mm size immediately after melt polymerization, and has residual solvent content of 300 ppm or less, based on the total weight of resin. | 12-27-2012 |
20130094285 | PHASE CHANGE MEMORY DEVICE HAVING MULTI-LEVEL AND METHOD OF DRIVING THE SAME - A phase change memory device having a multi-level and a method of driving the same are presented. The disclosed phase change memory device includes variable resistors and shifting units. The variable resistors are interchanged into set and reset states in response to an applied current. The shifting units, which are connected to the variable resistors, shift resistance distribution in the set and reset state of the variable resistors by a predetermined level. | 04-18-2013 |
20130115438 | POLYARYLENE SULFIDE HAVING EXCELLENT PROCESSABILITY AND PREPARATION METHOD THEREOF - The present invention relates to polyarylene sulfide, in which a ratio of a peak area of a polymer chain of a second polyarylene sulfide having a lower molecular weight than the maximum peak molecular weight to a peak area of a polymer chain of a first polyarylene sulfide having a higher molecular weight than the maximum peak molecular weight is 1.3 or less in the molecular weight distribution of the polyarylene sulfide, as measured by gel permeation chromatography using polystyrene as a standard, and a preparation method thereof. This polyarylene sulfide exhibits excellent processability and generates no burrs (flashes) or the like, and can satisfactorily mold a product requiring high molding precision. | 05-09-2013 |
20140166965 | RESISTIVE MEMORY DEVICE AND FABRICATION METHOD THEREOF - A resistive memory device may include a bottom structure, a memory cell structure disposed on the bottom structure, and a data storage material disposed to surround an outer sidewall of the memory cell structure. | 06-19-2014 |
20140204664 | METHOD OF DRIVING PHASE CHANGE MEMORY DEVICE CAPABLE OF REDUCING HEAT DISTURBANCE - A method of driving phase change memory device includes initializing all memory cells and programming individually at least two selected memory cells disposed at random positions, wherein the selected memory cells are selected among the initialized memory cells. | 07-24-2014 |
20140325120 | RESISTIVE MEMORY DEVICE AND OPERATION METHOD THEREOF - A resistive memory device includes a memory cell array including a unit memory cell coupled between a word line and a bit line, wherein the unit memory cell includes a data storage material and a non-silicon-substrate-based type bidirectional access device coupled in series, a path setting circuit coupled between the bit line and the word line, suitable for providing a program pulse toward the bit line or the word line based on a path control signal, a forward write command, and a reverse write command, and a control unit suitable for providing a write path control signal, a forward program command, and a reverse program command based on an external command signal. | 10-30-2014 |