Patent application number | Description | Published |
20090097313 | PAGE BUFFER, MEMORY DEVICE HAVING THE PAGE BUFFER AND METHOD OF OPERATING THE SAME - A page buffer includes a first latch coupled between a sensing node and a data input/output node for storing data to be programmed. The sensing node is coupled to a bit line corresponding to an MLC selected for programming. The data input/output node receives/outputs data. A second latch is coupled to the sensing node for performing a program, verifying or read operation. A first switching means is coupled between the first latch and the sensing node for transmitting data stored in the first latch to the bit line through the sensing node when the program operation is performed. A second switching means is coupled to a first node of the second latch and the sensing node for verifying a first program operation. A third switching means is coupled between a second node of the second latch and the sensing node for verifying a second program operation. | 04-16-2009 |
20090141561 | METHOD OF OPERATING A NON-VOLATILE MEMORY DEVICE - In a method of operating a non-volatile memory device subdivided verifications are performed by increasing verify voltages. Accordingly, threshold voltage distributions of memory cells can be narrowed and, therefore, the program performance of a flash memory device can be improved. | 06-04-2009 |
20090161443 | PAGE BUFFER OF NON-VOLATILE MEMORY DEVICE AND PROGRAMMING METHOD OF NON-VOLATILE MEMORY DEVICE - A page buffer includes a first register, a second register and a data I/O unit. The first register temporarily stores data to be programmed into cells included in a first memory cell block group, or reads and stores data of a corresponding memory cell. The second register temporarily stores data to be programmed into cells included in a second memory cell block group, or reads and stores data of a corresponding memory cell. The data I/O unit inputs specific data to the first register and the second register, or outputs data stored in the first register and the second register. | 06-25-2009 |
20090161444 | PAGE BUFFER AND PROGRAMMING METHOD OF A NON-VOLATILE MEMORY DEVICE - A page buffer includes a first ground voltage supply unit for applying a ground voltage to first and second registers according to a level of a sense node, and a second ground voltage supply unit for applying the ground voltage to the first and second registers irrespective of a level of the sense node. A method of programming a non-volatile memory device includes storing a high-level data in a first node of a first register of a plurality of page buffers, precharging a sense node with a high level, resetting the data stored in the first node of the first register according to a voltage level of the sense node, precharging the sense node with a high level, storing external data in the first node according to a voltage level of the sense node, and performing a program operation according to the data stored in the first node. | 06-25-2009 |
20090172482 | METHODS FOR PERFORMING FAIL TEST, BLOCK MANAGEMENT, ERASING AND PROGRAMMING IN A NONVOLATILE MEMORY DEVICE - Methods for performing a fail test, block management, erase operations and program operations are used in a nonvolatile memory device having a block switch devoid of a fuse and a PMOS transistor. A method for performing a fail test in a nonvolatile memory device includes performing a fail test for a memory cell block; storing good block information in a block information store associated with the corresponding block when the memory cell block is a good block; and repeating the performing and storing steps for all memory cell blocks. | 07-02-2009 |
20090279364 | METHOD OF PROGRAMMING IN A FLASH MEMORY DEVICE - A method of programming a flash memory device includes programming a first memory cell coupled to an even bit line by applying a first program voltage to a word line, and verifying whether the first memory cell is programmed through a first verifying voltage. The first program voltage that is repeatedly increased by a step voltage when the first memory cell is not programmed. A second memory cell coupled to an odd bit line is programmed by applying the first program voltage to the word line. Whether the second memory cell is programmed is verified using a second verifying voltage that is higher than the first verifying voltage. The second memory cell is programmed using a program voltage that is repeatedly increased by the step voltage when the second memory cell is not programmed. | 11-12-2009 |
20090290431 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a page buffer circuit. The page buffer circuit includes a memory cell area, a first bit line select unit, and a second bit line select unit. A plurality of memory cells of the memory cell area is connected by bit lines and word lines. The first bit line select unit i s connected to one or more bit lines of the memory cell area and is configured to precharge or discharge a selected bit line in response to a control signal. The second bit line select unit is connected to the same bit line as the first bit line select unit and is configured to precharge or discharge the selected bit line simultaneously with the first bit line select unit. | 11-26-2009 |
20100008137 | NONVOLATILE MEMORY DEVICE AND PROGRAM OR ERASE METHOD USING THE SAME - A nonvolatile memory device includes a comparison unit configured to compare a reference voltage and a voltage of each of a plurality of nodes of a sample memory cell string, a state storage unit configured to store state information of each of memory cells depending on the corresponding comparison result of the comparison unit, and a high voltage generation unit configured to change a program start voltage depending on data stored in the state storage unit. | 01-14-2010 |
20100302864 | METHOD OF OPERATING NONVOLATILE MEMORY DEVICE - A method of operating a nonvolatile memory device includes performing a reset operation for setting a level of a program voltage to a first level, performing a program operation and a verification operation on memory cells included in a first page of a first memory block while raising the program voltage from the first level, storing a level of the program voltage, supplied to the first page when memory cells programmed to have threshold voltages with at least a verification voltage are detected during the verification operation, as a second level, while raising the program voltage from the second level, performing the program operation and the verification operation on each of second to last pages of the first memory block, and after completing the program operation for the first memory block, performing the reset operation for setting the level of the program voltage to the first level. | 12-02-2010 |
20100302881 | VOLTAGE GENERATION CIRCUIT AND NONVOLATILE MEMORY DEVICE USING THE SAME - A voltage generation circuit comprises a voltage generation control unit configured to output one of a first voltage level determination signal having a fixed data value and a second voltage level determination signal having a varying data value in response to a selection signal, and a voltage generation unit configured to generate a voltage having a single pulse form or a voltage having a pulse form whose rising edge portion rises in incremental voltage steps in response to the voltage level determination signal outputted from the voltage generation control unit. | 12-02-2010 |
20100306579 | NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A nonvolatile memory device and its programming method includes a memory block having a number of memory cells, a page buffer unit coupled to the memory block and configured to temporarily store program data, to transmit the program data to the memory block, to perform a program operation for the program data, and to output the stored program in response to the memory block being treated as being a bad block, and a control unit configured to transmit the program data to the memory block, temporarily store the program data outputted from the page buffer unit, and transmit the stored program data to another page buffer unit coupled to another memory block. | 12-02-2010 |
20100309727 | METHOD OF OPERATING MEMORY DEVICE HAVING PAGE BUFFER - A method of verifying data in a memory device having a page buffer for performing a program operation, a verifying operation and a read operation, includes: storing data to be programmed in a multi level cell of a first latching circuit in the page buffer; storing reference data set for the verifying operation in a second latching circuit; programming the data stored in the first latching circuit to the multi level cell; and verifying the programming of the data through a first node or a second node in the second latching circuit in accordance with a verifying voltage. | 12-09-2010 |
20110141809 | PAGE BUFFER OF NON-VOLATILE MEMORY DEVICE AND PROGRAMMING METHOD OF NON-VOLATILE MEMORY DEVICE - Multi-level cell programming methods are provided. A method includes providing a page buffer including first and second registers connected to first and second memory cell blocks, respectively. A least significant bit (LSB) program of each memory cell is completed. Most significant bit (MSB) data is set in a first node of the first register. An MSB program is performed. When the MSB program is performed at a first verify voltage, first data at a first voltage level is set in the first node. When the MSB program is performed at a second verify voltage, second data at a second voltage level, opposite to the first voltage level, is set in the first node. When the MSB program is performed at a third verify voltage, the first data is set in the first node. The MSB program is repeated according to the first node data. | 06-16-2011 |
20140189407 | DATA STORAGE DEVICE AND METHOD FOR OPERATING THE SAME - A data storage device and a method for operating the same are provided. In the data storage device and the method for operating the same, a predetermined number of memory chips are operated based on a usable power limitation when a power supply is supplied from a finite power supply source such as a battery, and as many memory chips as possible are operated in parallel. Accordingly, performance of the data storage device may be improved. | 07-03-2014 |