Patent application number | Description | Published |
20080209096 | STRUCTURE FOR INITIALIZING EXPANSION ADPATERS INSTALLED IN A COMPUTER SYSTEM HAVING SIMILAR EXPANSION ADAPTERS - A design structure embodied in a machine readable storage medium for at designing, manufacturing, and/or testing a design is disclosed for initializing expansion adapters installed in a computer system having similar expansion adapters that include detecting an expansion adapter installed in a computer system having a plurality of expansion adapters, the detected expansion adapter having an option ROM containing initialization code, identifying similar expansion adapters installed in the computer system that correspond to the detected expansion adapter, each of the identified similar expansion adapters having an option ROM containing initialization code, disabling the option ROM of each of the identified similar expansion adapters, and initializing the plurality of expansion adapters installed in the computer system without executing the initialization code of the identified similar expansion adapters. | 08-28-2008 |
20080219461 | SYSTEM FOR MONITORING AUDIBLE TONES IN A MULTIPLE PLANAR CHASSIS - Aspects for monitoring audible tones indicative of operational status of each planar in a multiple planar chassis are described. Included in the aspects is the monitoring of a speaker channel of each planar of a plurality of planars in a common chassis for state changes of beep tones. An operational status of a specific planar emitting the beep tones is identified based on the state changes. | 09-11-2008 |
20090113197 | EXPEDIENT PREPARATION OF MEMORY FOR VIDEO EXECUTION - A computer system that initializes a fraction of the computer system's memory for execution of video during booting of the computer system is provided. The computer system can include a first portion of BIOS code on a ROM device, wherein the first portion includes instructions for initializing the fraction. The computer system further can include a second portion of BIOS code that copies itself to the fraction upon completion of initialization of the fraction, wherein the second portion executes on the fraction and wherein the second portion initializes system memory and initializes a video buffer. The computer system further can include a copy of the second portion located on the ROM device, wherein the copy of the second portion executes until video buffer initialization is completed but before all of the system memory is initialized. Further, the video buffer displays video before all of the computer system's memory is initialized. | 04-30-2009 |
20090150721 | Utilizing A Potentially Unreliable Memory Module For Memory Mirroring In A Computing System - Methods, apparatus, and products are disclosed for utilizing a potentially unreliable memory module for memory mirroring in a computing system, the computing system including at least two memory modules, that includes: retrieving error information from an error log stored in non-volatile memory, the error information describing an occurrence of a correctable memory error on one of the memory modules; determining whether a memory mirroring mode is enabled for the computing system, the memory mirroring mode specifying that memory contents are mirrored on the two memory modules; and utilizing, in dependence upon the error information, the memory module on which the correctable memory error occurred to mirror the memory contents if the memory mirroring mode is enabled. | 06-11-2009 |
20100125731 | METHOD FOR SECURELY MERGING MULTIPLE NODES HAVING TRUSTED PLATFORM MODULES - Method, apparatus and computer program product are provided for operating a plurality of computer nodes while maintaining trust. A primary computer node and at least one secondary computer node are connected into a cluster, wherein each of the clustered computer nodes includes a trusted platform module (TPM) that is accessible to software and includes security status information about the respective computer node. Each clustered computer node is then merged into a single node with only the TPM of the primary computer node being accessible to software. The TPM of the primary computer node is updated to include the security status information of each TPM in the cluster. Preferably, the step of merging is controlled by power on self test (POST) basic input output system (BIOS) code associated with a boot processor in the primary node. | 05-20-2010 |
20100325404 | Updating Programmable Logic Devices - Updating programmable logic devices (‘PLDs’) in a symmetric multiprocessing (‘SMP’) computer, each compute node of the SMP computer including a PLD coupled for data communications through a bus adapter, the bus adapter adapted for data communications through a set of one or more input/output (‘I/O’) memory addresses, including configuring the primary compute node with an update of the configuration instructions for the PLDs; assigning, by the PLDs at boot time in an SMP boot, a unique, separate set of one or more I/O addresses to each bus adapter on each compute node; and providing, by the primary compute node during the SMP boot, the update to all compute nodes, writing the update as a data transfer to each of the PLDs through each bus adapter at the unique, separate set of one or more I/O addresses for each bus adapter. | 12-23-2010 |
20110010584 | Diagnosis of and Response to Failure at Reset in a Data Processing System - Detection of a reset failure in a multinode data processing system is provided by a diagnostic circuit in each of a plurality of the server nodes of the system. Each diagnostic circuit is coupled to a code fetch chain of its corresponding node. At reset, prior to a node processor retrieving startup code from the code fetch chain, the diagnostic circuit provides diagnostic signals to the code fetch chain. A problem in the code fetch chain is detected from a response to the diagnostic signals. When a problem is detected, a node failure status for the problem node may be signaled to the other nodes. The multinode system may be configured in response to signaled node failure status, such as by dropping failed nodes and replacing a failed primary node with a secondary node if necessary. | 01-13-2011 |
20120166113 | DETECTING USE OF A PROPER TOOL TO INSTALL OR REMOVE A PROCESSOR FROM A SOCKET - Method and apparatus to detect use of a manufacturer-approved insertion tool to connect a processor into electronic communication with a land grid array socket on a circuit board of a computer. A baseboard management controller electronically coupled to electrical contacts on the circuit board engages a conductor on the manufacturer-approved insertion tool and records the event. | 06-28-2012 |
20120201392 | System For Monitoring Audible Tones In A Multiple Planar Chassis - Aspects for monitoring audible tones indicative of operational status of each planar in a multiple planar chassis are described. Included in the aspects is the monitoring of a speaker channel of each planar of a plurality of planars in a common chassis for state changes of beep tones. An operational status of a specific planar emitting the beep tones is identified based on the state changes. | 08-09-2012 |
20120204021 | Updating Programmable Logic Devices - Updating programmable logic devices (‘PLDs’) in a symmetric multiprocessing (‘SMP’) computer, each compute node of the SMP computer including a PLD coupled for data communications through a bus adapter, the bus adapter adapted for data communications through a set of one or more input/output (‘I/O’) memory addresses, including configuring the primary compute node with an update of the configuration instructions for the PLDs; assigning, by the PLDs at boot time in an SMP boot, a unique, separate set of one or more I/O addresses to each bus adapter on each compute node; and providing, by the primary compute node during the SMP boot, the update to all compute nodes, writing the update as a data transfer to each of the PLDs through each bus adapter at the unique, separate set of one or more I/O addresses for each bus adapter. | 08-09-2012 |