Sauter, US
Donald A. Sauter, Victoria, MN US
Patent application number | Description | Published |
---|---|---|
20140157573 | METHOD OF MANUFACTURING A PEELABLE ATRAUMATIC TIP AND BODY FOR A CATHETER OR SHEATH - A method of manufacturing a splittable/peelable tubular body of a catheter or sheath wherein the tubular body has a splittable/peelable atraumatic tip is disclosed. The atraumatic tip is generally softer than the tubular body. The tubular body and atraumatic tip each comprise a peel mechanism longitudinally extending along their respective lengths. The peel mechanisms are formed by longitudinally extending regions of interfacial bonding between first and second longitudinally extending strips of polymer material. Each strip forms at least a portion of an outer circumferential surface of the tubular body and atraumatic tip. A region of stress concentration extends along the region of interfacial bonding. The stress concentration facilitates the splitting of the tubular body and atraumatic tip along their respective peel mechanisms. | 06-12-2014 |
Edward R. Sauter, Columbia, MO US
Patent application number | Description | Published |
---|---|---|
20080293161 | Detection of Carbohydrate Biomarkers - The present invention generally relates to detection of carbohydrate biomarkers in nipple aspirate fluid samples. One aspect of the invention is a method for assaying a nipple aspirate fluid for the presence of TF or Tn carbohydrate biomarker. The assay generally employs an immobilized capture agent specific for TF or Tn and can be further coupled to either direct or indirect detection of bound TF or Tn carbohydrate biomarker through the use of a labeled binding agent. | 11-27-2008 |
Edward R. Sauter, Tyler, TX US
Patent application number | Description | Published |
---|---|---|
20140038211 | BREAST CANCER DIAGNOSIS USING NIPPLE DISCHARGE - A panel of biomarkers for the prediction of breast cancer using nipple discharge, as well as method and kits for using the same. Nipple discharge may be nipple aspirate fluid or spontaneous discharge. The panel has been selected to optimize predictive ability while minimizing the number of markers to be screened. As observed, the panel approaches one hundred percent accuracy for predicting breast cancer without the need for invasive biopsy. | 02-06-2014 |
George U. Sauter, Malvern, PA US
Patent application number | Description | Published |
---|---|---|
20090307120 | METHOD OF CONSTRUCTING A STOCK INDEX - Computer-implemented methods of creating and maintaining stock indexes are provided. For a stock index of a particular size, a band is defined around the upper and/or lower limits of the stock index. To be added to, or dropped from, a particular stock index, the stocks must fall outside of the bands for that particular stock index size. Stock migration is controlled using a systematic stock migration process so that stocks are gradually added and deleted from an index. Stock investment style is determined in a multi-dimensional process, instead of a linear process. Furthermore, the number of stocks in the stock index need not be a fixed value, but may depend upon how many stocks meet predefined criteria at any given point in time. | 12-10-2009 |
20100223202 | COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING INVESTMENT COMPANY THAT ISSUES A CLASS OF CONVENTIONAL SHARES AND A CLASS OF EXCHANGE-TRADED SHARES IN THE SAME FUND - A computer program product is provided for administering a single investment company. The computer program product has a computer-readable medium encoded with computer-executable instructions. The instructions perform a method wherein the single investment company issuing one or more classes of shares that are bought from and redeemed with the single investment company at a net asset value and issues one or more classes of shares that are listed for trading on a securities exchange and that are bought and sold at negotiated market prices. One or more computers maintain account data of the outstanding shares. An owner of any share of any share class has an undivided interest in the single investment company. | 09-02-2010 |
20110258089 | INVESTMENT COMPANY THAT ISSUES A CLASS OF CONVENTIONAL SHARES AND A CLASS OF EXCHANGE-TRADED SHARES IN THE SAME FUND - An automated method is provided for administering a single investment company that issues one or more classes of shares that are bought from and redeemed with the single investment company at a net asset value and issues one or more classes of shares that are listed for trading on a securities exchange and that are bought and sold at negotiated market prices. One or more computers maintain account data of the outstanding shares. An owner of any share of any share class has an undivided interest in the single investment company. | 10-20-2011 |
20120101962 | INVESTMENT COMPANY THAT ISSUES A CLASS OF CONVENTIONAL SHARES AND A CLASS OF EXCHANGE-TRADED SHARES IN THE SAME FUND - An automated method is provided for administering a single investment company that issues one or more classes of shares that are bought from and redeemed with the single investment company at a net asset value and issues one or more classes of shares that are listed for trading on a securities exchange and that are bought and sold at negotiated market prices. One or more computers maintain account data of the outstanding shares. An owner of any share of any share class has an undivided interest in the single investment company. | 04-26-2012 |
20120278259 | Computer-implemented method of constructing a stock index using index rotation - Computer-implemented methods of creating and maintaining stock indexes are provided. Stock migration is controlled using a systematic stock migration process so that stocks are gradually added and deleted from an index. | 11-01-2012 |
20120278260 | Computer-implemented method of constructing a stock index using multi-dimensional delineation between value and growth - Computer-implemented methods of creating and maintaining stock indexes are provided. Stock investment style is determined in a multi-dimensional process, instead of a linear process. Furthermore, the number of stocks in the stock index need not be a fixed value, but may depend upon how many stocks meet predefined criteria at any given point in time. | 11-01-2012 |
20130275333 | METHOD FOR IMPLEMENTING AN INVESTMENT COMPANY THAT ISSUES A CLASS OF CONVENTIONAL SHARES AND A CLASS OF EXCHANGE-TRADED SHARES IN THE SAME FUND - A method is provided for administering a single investment company that issues one or more classes of shares that are bought from and redeemed with the single investment company at a net asset value and issues one or more classes of shares that are listed for trading on a securities exchange and that are bought and sold at negotiated market prices. One or more computers maintain account data of the outstanding shares. An owner of any share of any share class has an undivided interest in the single investment company. | 10-17-2013 |
20140195404 | METHOD AND SYSTEM FOR IMPLEMENTING AN INVESTMENT COMPANY THAT ISSUES A CLASS OF CONVENTIONAL SHARES AND A CLASS OF EXCHANGE-TRADED SHARES IN THE SAME FUND - A method is provided for administering a single investment company that issues one or more classes of shares that are bought from and redeemed with the single investment company at a net asset value and issues one or more classes of shares that are listed for trading on a securities exchange and that are bought and sold at negotiated market prices. One or more computers maintain account data of the outstanding shares. An owner of any share of any share class has an undivided interest in the single investment company. | 07-10-2014 |
Guenter A. Sauter, Ridgefield, CT US
Patent application number | Description | Published |
---|---|---|
20100106747 | DYNAMICALLY BUILDING AND POPULATING DATA MARTS WITH DATA STORED IN REPOSITORIES - Methods, systems, and articles of manufacture for constructing and populating data marts with dimensional data models from a set of data repositories that contain factual and association information about a set of related assets are disclosed. An intermediate data warehouse is generated to process the facts and associations for each asset. Using the intermediate warehouse, one or more data marts are generated with fact tables, dimensions, and hierarchies to fully model the information available for each asset. | 04-29-2010 |
20100312737 | Semi-Automatic Evaluation and Prioritization of Architectural Alternatives for Data Integration - A systematic approach to evaluating and prioritizing architectural design pattern alternatives for data integration. A set of decision factors is derived from requirements for a system to be integrated. A default score is assigned to each decision factor based on historical data integration knowledge, and the default scores are weighted. A priority score is also assigned to each decision factor based on collected inputs from system metadata and subject matter experts in the enterprise system. Next, an individual consolidated score for each decision factor is calculated using the default score, the weighted score, and the priority score, and a total consolidated score is calculated from the individual consolidated scores for the architecture design pattern. The total consolidated score for the architecture design pattern may be compared against total consolidated scores for other architecture design patterns to determine a suitable candidate architecture design pattern for data integration. | 12-09-2010 |
20110320985 | INFORMATION LANDSCAPE MODELING, ANALYSIS & VALIDATION - Managing and validating a project using an information landscape. Embodiments include providing an information landscape including a topology of landscape elements for the project, linking the topology of landscape elements to a plurality of solution artifacts, and validating at least one of the plurality of solution artifacts and semantics of the information landscape. | 12-29-2011 |
20120197654 | INFORMATION LANDSCAPE MODELING, ANALYSIS & VALIDATION - Managing and validating a project using an information landscape. Embodiments include providing an information landscape including a topology of landscape elements for the project, linking the topology of landscape elements to a plurality of solution artifacts, and validating at least one of the plurality of solution artifacts and semantics of the information landscape. | 08-02-2012 |
Guenter Anton Sauter, Ridgefield, CT US
Patent application number | Description | Published |
---|---|---|
20100106558 | Trust Index Framework for Providing Data and Associated Trust Metadata - An approach is provided in which facts are received and then one or more atomic fact trust analyses are performed on the facts. The atomic fact trust analyses result in various atomic trust factor scores. Composite trust analysis is performed using the atomic trust factor scores. The composite trust analyses result in composite trust factor scores. The atomic trust factor scores and the composite trust factor scores are stored in a trust index repository that is managed by a trust index framework. A request is then received for trusted data, the request being from an information consumer. The trust index framework then retrieves one of the composite trust factor scores from the trust index repository, with the retrieved composite trust factor score corresponding to the trusted data request, and this the retrieved composite trust factor score is provided to the information consumer. | 04-29-2010 |
20100106559 | Configurable Trust Context Assignable to Facts and Associated Trust Metadata - An approach is provided for selecting a trust factor from trust factors that are included in a trust index repository. A trust metaphor is associated with the selected trust factor. The trust metaphor includes various context values. Range values are received and the trust metaphor, context values, and range values are associated with the selected trust factor. A request is received from a data consumer, the request corresponding to a trust factor metadata score that is associated with the selected trust factor. The trust factor metadata score is retrieved and matched with the range values. The matching results in one of the context values being selected based on the retrieved trust factor metadata score. The selected context value is then provided to the data consumer. | 04-29-2010 |
20100106560 | Generating Composite Trust Value Scores Based on Assignable Priorities, Atomic Metadata Values and Associated Composite Trust Value Scores - An approach is provided in which atomic trust scores are computed using a atomic trust factors that are applied to a plurality of metadata. A first set of composite trust scores are computed using some of the atomic trust scores. The composite trust scores are computed using a first set of algorithms. Some of the algorithms use a factor weighting value as input to the algorithm. A second plurality of composite trust scores is computed using some of the composite trust scores that were included in the first set of scores as input. A fact and one of the second set of composite trust scores are presented to a user. The presented composite trust score provides a trustworthiness value that corresponds to the presented fact. | 04-29-2010 |
20100107244 | Trust Event Notification and Actions Based on Thresholds and Associated Trust Metadata Scores - An approach is provided for selecting one or more trust factors from trust factors included in a trust index repository. Thresholds are identified corresponding to one or more of the selected trust factors. Actions are identified to perform when the selected trust factors reach the corresponding threshold values. The identified thresholds, identified actions, and selected trust factors are stored in a data store. The selected trust factors are monitored by comparing one or more trust metadata scores with the stored identified thresholds. The stored identified actions that correspond to the selected trust factors are performed when one or more of the trust metadata scores reach the identified thresholds. At least one of the actions includes an event notification that is provided to a trust data consumer. | 04-29-2010 |
Guenter Anton Sauter, Somers, NY US
Patent application number | Description | Published |
---|---|---|
20110113001 | Information Integrity Rules Framework - An information integrity rules framework manages rules across heterogeneous enforcement systems by managing canonical rules that are mapped to native rules and enforcement system-specific rules. The information integrity rules framework discovers an existing native rule utilized by an enforcement system, which is written in an enforcement system-specific format. Next, the information integrity rules framework creates a mapping entry and maps the native rule to a canonical rule, which is independent from the enforcement system. When the information integrity rules framework detects a change to one of the rules managed by the framework, the information integrity rules framework propagates the change to other corresponding rules across enforcement systems managed by the framework. | 05-12-2011 |
20120166406 | Information Integrity Rules Framework - An information integrity rules framework manages rules across heterogeneous enforcement systems by managing canonical rules that are mapped to native rules and enforcement system-specific rules. The information integrity rules framework discovers an existing native rule utilized by an enforcement system, which is written in an enforcement system-specific format. Next, the information integrity rules framework creates a mapping entry and maps the native rule to a canonical rule, which is independent from the enforcement system. When the information integrity rules framework detects a change to one of the rules managed by the framework, the information integrity rules framework propagates the change to other corresponding rules across enforcement systems managed by the framework. | 06-28-2012 |
Ingo Sauter, Aberdeen, NC US
Patent application number | Description | Published |
---|---|---|
20080274857 | Method for Controlling an Automatic Vehicle Transmission in Order to Reduce Back-and-Forth Shifting - A method of controlling an automatic transmission of a motor vehicle having clutches controlled by an electronic control unit. A transmission rotational speed in an initial transmission stage is determined. If a first transmission shifting rotational speed is reached, the transmission is shifted from the initial transmission stage to a target transmission stage. A target transmission rotational speed of the target transmission stage is then ascertained. A difference is next ascertained between the target transmission rotational speed and a second shifting transmission rotational speed. An initial counter value, of a counter, is determined, which depends on the transmission rotational speed difference. The counter is next caused to carry out counting, from the initial counter value, as time progresses. If and when the counter value reaches zero, the transmission is shifted from the target transmission stage toward the initial transmission stage. | 11-06-2008 |
Ingo Sauter, D-Aberdeen, NC US
Patent application number | Description | Published |
---|---|---|
20090265067 | Method for Controlling Shifting of a Stepped Automatic Transmission - A method for controlling gear shifts in an automated stepped gear transmission of a motor vehicle in which operating parameters of the motor vehicle are continuously determined and evaluated for initiating and carrying out a shift from a currently engaged gear to a target gear such that, before a shift, the shift speed for initiating the shift and the target gear are determined. For better adaptation of the shift, in particular the determination of the shift speed and the target gear, to the current driving and operating conditions of the motor vehicle, the shift types “shift-speed-orientated shift” and “target-speed-orientated shift” are provided and, immediately before a shift operation, it is decided, as a function of at least one of the operating parameters in which, of the two shift types, the shift is to be carried out. | 10-22-2009 |
Ingo-Gerd Sauter, Aberdeen, NC US
Patent application number | Description | Published |
---|---|---|
20080300746 | System for preventing damage to a vehicle - A system for preventing damage to a vehicle, such as a truck, is provided. A sensor may be operable to measure a parameter relating to a component in a vehicle and to provide a parameter signal indicative of the measured parameter. A processor may be in communication with the sensor and operable to receive the parameter signal from the sensor. The processor may be further operable to analyze the parameter signal. The processor may be further operable to initiate a damage prevention process including a reduction of heat generation in the vehicle based on the parameter. | 12-04-2008 |
20090192760 | SYSTEM FOR ESTIMATING A VEHICLE MASS - A vehicle mass estimation system for use in a vehicle, such as a truck, including a transmission is provided. A processor may be operable to receive a signal relating to a mass of at least a portion of the vehicle. The processor may be further operable to estimate a vehicle mass based, at least in part, on the signal. The processor may be further operable to select a desired gear ratio for engagement in a transmission based, at least in part, on the estimated vehicle mass. | 07-30-2009 |
20110004382 | SYSTEM FOR ESTIMATING A VEHICLE MASS - A vehicle mass estimation system for use in a vehicle, such as a truck, including a transmission is provided. A processor may be operable to receive a signal relating to a mass of at least a portion of the vehicle. The processor may be further operable to estimate a vehicle mass based, at least in part, on the signal. The processor may be further operable to select a desired gear ratio for engagement in a transmission based, at least in part, on the estimated vehicle mass. | 01-06-2011 |
20110015808 | SYSTEM FOR ESTIMATING A VEHICLE MASS - A vehicle mass estimation system for use in a vehicle, such as a truck, including a transmission is provided. A processor may be operable to receive a signal relating to a mass of at least a portion of the vehicle. The processor may be further operable to estimate a vehicle mass based, at least in part, on the signal. The processor may be further operable to select a desired gear ratio for engagement in a transmission based, at least in part, on the estimated vehicle mass. | 01-20-2011 |
James F. Sauter, Cleburne, TX US
Patent application number | Description | Published |
---|---|---|
20120312373 | Solar Roof Panel Assembly and Method for Installation - A solar roof panel assembly for new construction or retrofit installation above a roof deck of a building structure comprises a metal roof panel base, at least one solar cell, a stone coating, and an electrical junction box fastened to the back of the metal roof panel base. The electrical junction box houses electrical components connected to the solar cell, and electrical connection elements extend from the electrical junction box. The solar roof panel assembly may be installed such that an air gap is created between the solar roof panel assembly and the roof deck, and cabling and other electrical components may be placed in the air gap. Multiple solar roof panel assemblies may be interconnected. A solar roof panel assembly may replace a previously-installed roof panel, and may be aesthetically and/or structurally similar to adjacent previously-installed roof panels. | 12-13-2012 |
Jeff Sauter, Lowville, NY US
Patent application number | Description | Published |
---|---|---|
20150233435 | INTEGRATED SLACK ADJUSTER WITH IMPROVED ENVIRONMENTAL PROTECTION - Embodiments of the invention provide one or more of the following features or combinations of such features to slack adjusters: rubber boots or bellows on either end of the slack adjuster to shed water away from the slack adjuster; a center vent and wasp excluder to vent any water build up in the slack adjuster clutch area; an added seal and wear ring at the slack adjuster end cap; and increased corrosion and wear protection for the rod. | 08-20-2015 |
Jeffrey Sauter, Lowville, NY US
Patent application number | Description | Published |
---|---|---|
20140353095 | Slack Adjuster Environmental Improvements - A slack adjuster that is protected against environmental contaminants via a series of holes positioned circumferentially around each end and covered by a sleeve having a slot is aligned with one of the series of holes while covering the remaining holes. The sleeve protects against infiltration of contaminants at the ends of the slack adjuster and allows any contaminants that do infiltrate the slack adjuster to be expelled through the aligned hole and slot. The central portion of the slack adjuster may also be protected by including a series of circumferential holes that are selectively covered by a sleeve having a drain positioned to align with the lowest holes while covering the remaining holes. | 12-04-2014 |
Jeffrey F. Sauter, Lowville, NY US
Patent application number | Description | Published |
---|---|---|
20100193755 | RAIL HANDBRAKE WITH PROLONGED RELEASE - A hand brake actuator for a rail car has a rotary input connected to a rotary output by a transmission including a clutch and a ratchet wheel and pawl, a declutching mechanism for disengaging the clutch in a declutched position of the declutching mechanism, and a release handle with a first cam which drives the declutching mechanism to the declutched position when the release handle is moved from an apply position to a release position. A second cam is biased in a first direction to engage and retain the declutching mechanism in a declutched position after the release handle is removed from the release position. A follower is connected to the second cam and is responsive to the rotation of the input in an apply direction to rotate the second cam in a second direction opposite the first direction to release the declutching mechanism and allow the clutch to reengage. | 08-05-2010 |
20110108374 | AUTOMATIC RELEASE HAND BRAKE CONTROL SYSTEM - In a rail vehicle hand brake having a release activated by a pneumatic cylinder, the present control system includes a manual valve having an output connected to a source of pressure at an input when manually activated. A volume is to be charged by the source of pressure. A choke connects the volume to exhaust. The volume and the choke prolong the time the source of pressure is connected to the pneumatic cylinder after the manual valve is activated. | 05-12-2011 |
20110108376 | BOLSTER MOUNTED BRAKE SYSTEM - A brake system includes a brake cylinder having a piston rod and a brake lever connecting the piston rod to a brake beam and a slack adjuster. An actuating lever is connected to the brake beam and the brake cylinder. A trigger of the slack adjuster is connected to the actuating lever. The actuating lever is pivotally and rotationally connected to the brake beam and swivelably connected to the brake cylinder. Also, a piston stoke indictor including an indicia positioned on a support structure of a brake cylinder to be adjacent the end of a portion of a brake piston at its extended position. | 05-12-2011 |
20110232370 | TEST PORT ADAPTER FOR EP OVERLAY - A test port adapter plate is used with an electropneumatic overlay access plate, which is incorporated to the single-sided pipe bracket in an overlay system, to provide enough space for a test connector to be connected. | 09-29-2011 |
20140284153 | Automatic Release Hand Brake Control System - In a rail vehicle hand brake having a release activated by a pneumatic cylinder, the present control system includes a manual valve having an output connected to a source of pressure at an input when manually activated. A volume is to be charged by the source of pressure. A choke connects the volume to exhaust. The volume and the choke prolong the time the source of pressure is connected to the pneumatic cylinder after the manual valve is activated. | 09-25-2014 |
20150246680 | Brake Beam Wear Liner - A brake beam wear liner having a base wall extending along a first plane and first and second opposing side walls that extend obliquely from the base wall along second and third planes to be outwardly offset a predetermined angle. One or more detents may be positioned on the outside of the side walls to maintain the offset angle after installation in a brake beam bracket. The base wall and the first and second opposing walls, as well as first and second flanges extending from the sides walls preferably have a uniform thickness. | 09-03-2015 |
Jeffrey L. Sauter, State College, PA US
Patent application number | Description | Published |
---|---|---|
20120213515 | SERVICE GROUP AGGREGATION - Methods and systems for aggregating service groups are provided. A chain of fiber nodes in a DOCSIS system is formed to aggregate the service groups served by the fiber nodes to form a super-service group. Multiple channels of a multiplexed data stream are used to transmit the signals from the super-service group. By creating a chain of fiber nodes and using multiple channels to transmit the signals from the super-service group, a DOCSIS system can be more efficiently reconfigured to segment a super-service group once the system has become exhausted. | 08-23-2012 |
John A. Sauter, Ann Arbor, MI US
Patent application number | Description | Published |
---|---|---|
20110178978 | CHARACTERIZING AND PREDICTING AGENTS VIA MULTI-AGENT EVOLUTION - A method of predicting the behavior of software agents in a simulated environment involving modeling a plurality of software agents representing entities to be analyzed, which may be human beings. Using a set of parameters that governs the behavior of the agents, the internal state of at least one of the agents is estimated by its behavior in the simulation, including its movement within the environment. This facilitates a prediction of the likely future behavior of the agent based solely upon its internal state; that is, without recourse to any intentional agent communications. In one embodiment, the simulated environment is based upon a digital pheromone infrastructure. The simulation integrates knowledge of threat regions, a cognitive analysis of the agent's beliefs, desires, and intentions, a model of the agent's emotional disposition and state, and the dynamics of interactions with the environment. | 07-21-2011 |
Joseph A. Sauter, Arvada, CO US
Patent application number | Description | Published |
---|---|---|
20100262043 | ANNULOPLASTY SIZERS FOR MINIMALLY INVASIVE PROCEDURES - A sizing plate for sizing a native valve annulus in a patient's heart for either valve replacement or repair during a minimally invasive surgical procedure is shown and described. The sizing plate is generally shaped such that it corresponds to the shape of the native valve annulus. Additionally, a thickness of the sizing plate is such that it can be inserted through a space between the ribs of the patient during the procedure. The sizing plate includes two keyways extending though the plate separated by a bridge. The keyways are sized and shaped such that they are adapted to be engaged by a minimally invasive surgical tool such as a laparoscopic grasper. The keyways in conjunction with the bridge facilitate manipulation of the sizing plate by the grasper from an external location. | 10-14-2010 |
20140046219 | ANNULOPLASTY SIZERS FOR MINIMALLY INVASIVE PROCEDURES - A sizing plate for sizing a native valve annulus in a patient's heart for either valve replacement or repair during a minimally invasive surgical procedure is shown and described. The sizing plate is generally shaped such that it corresponds to the shape of the native valve annulus. Additionally, a thickness of the sizing plate is such that it can be inserted through a space between the ribs of the patient during the procedure. The sizing plate includes two keyways extending though the plate separated by a bridge. The keyways are sized and shaped such that they are adapted to be engaged by a minimally invasive surgical tool such as a laparoscopic grasper. The keyways in conjunction with the bridge facilitate manipulation of the sizing plate by the grasper from an external location. | 02-13-2014 |
Karl Sauter, Pleasanton, CA US
Patent application number | Description | Published |
---|---|---|
20150362547 | Step Drill Test Structure of Layer Depth Sensing on Printed Circuit Board - A step drill test structure for a PCB and method for using the same is disclosed. In one embodiment, a test structure includes a drill path and a connection via. The drill path may include sensing pads on selected ones of a plurality of layers of the PCB (e.g., the non-surface layers). The sensing pads of a given drill path may be electrically conductive, while the remaining portion of the drill path is non-conductive. The sensing pads of each drill path may be electrically coupled to the connection via. The depth of a given layer at a particular drill path may be determined by drilling, using an electrically conductive drill bit, into the drill path and determining when an electrical connection is made between the drill bit and the connection via. | 12-17-2015 |
Karl A. Sauter, Pleasanton, CA US
Patent application number | Description | Published |
---|---|---|
20100236823 | RING OF POWER VIA - Systems and methods for providing plated through-holes (PTH) in PCBs, which advantageously allow improved soldering capabilities, are described herein. Such systems and methods are achieved by reducing the heat sinking effects of PTHs by providing one or more vias surrounding the PTHs to provide an electrical connection between the PTH and the internal and bottom conductive layers of a PCB. In this regard, the PTHs are spaced apart from at least one of the internal conductive layers (e.g., ground or power layers), so the heat sinking effects are reduced. This feature enables molten solder to substantially fill the entire PTH before freezing, thereby improving the mechanical and electrical connection between an electrical component and the PCB. | 09-23-2010 |
Ken Sauter, Garland, TX US
Patent application number | Description | Published |
---|---|---|
20140095217 | Online Booking System - An online booking system includes a computer connected to a wide-area network, the computer including a processor and a memory configured to store programming and data. An act database includes entertainment records associated with a plurality of entertainers. Programming causes the processor to receive a performance request from a talent buyer over the network, the performance request including performance request data regarding an open performance date desired to be booked. The system determines if the performance request data matches a respective entertainment record in the act database and, if so, notifies a respective entertainer associated with the selected act to contact the buyer. If the act is booked, the processor updates the act and talent buyer itinerary databases. Matching a performance request with entertainment records may include determining if an entertainer is available within a predetermined number of days of the performance date and within a predetermined distance. | 04-03-2014 |
Ken E. Sauter, Goldsboro, NC US
Patent application number | Description | Published |
---|---|---|
20110116288 | APPARATUS FOR PROVIDING ZERO STANDBY POWER CONTROL IN AN APPLIANCE - An apparatus is provided that includes first and second switches in line between an appliance and terminals of the appliance that are connectable to a power source. The first switched is configured to open and close based on closing and opening of a door of the appliance, and the second switch is configured to open and close based on the mode of the appliance. Thus, the appliance may be connected to the power source when the first switch or the second switch is closed, and disconnected from the power source when both the first switch and the second switch are open. The apparatus further includes a third switch connected to the second switch and configured to control the second switch to close upon actuation of the third switch by a user, where actuation of the third switch may cause the appliance to enter an operational mode. | 05-19-2011 |
Kenneth Sauter, Sudbury, MA US
Patent application number | Description | Published |
---|---|---|
20140025721 | METHODS AND SYSTEMS FOR DYNAMICALLY PROVISIONING RESOURCES FOR ON-DEMAND COURSES - A method for providing access to dynamically provisioned resources and on-demand courses includes receiving, by an instantiation engine executing on a first computing device, from a second computing device associated with a user, an indication that the user has purchased access to the course at a scheduled time. A type of computing resource is identified for use during the course at the scheduled time. A service provider computing device is selected from a plurality of service provider computing devices, based upon an ability to provide access to the identified type of computing resource at the scheduled time. Before the scheduled time, the instantiation engine instructs the selected service provider computing device to provision a computing resource of the identified type. The method includes transmitting, to the second computing device, an instruction to establish a connection to the provisioned computing resource at the scheduled time. | 01-23-2014 |
20140025827 | METHODS AND SYSTEMS FOR DYNAMICALLY PROVISIONING RESOURCES FOR ON-DEMAND COURSES - A method for creating a course for dynamic provisioning includes receiving, by a creation engine, from a second computing device associated with a user, a request to create a course. The creation engine receives, from the second computing device, an identification of a type of computing resource for use during the course. A service provider computing device is selected from a plurality of service provider computing devices based upon an ability to provide access to the identified type of computing resource. The service provider computing device is instructed to provision a computing resource of the identified type. The second computing device is directed to connect to the provisioned computing resource. The method includes receiving, from the second computing device, an indication that the user configured the provisioned computing resource for use during the course. A state management engine is directed to save a state of the provisioned computing resource. | 01-23-2014 |
Kenneth W. Sauter, Garland, TX US
Patent application number | Description | Published |
---|---|---|
20090052024 | CLIP-ON NIGHT VISION DEVICE - A night viewer ( | 02-26-2009 |
Kurt Sauter, Thousand Oaks, CA US
Patent application number | Description | Published |
---|---|---|
20090022114 | ACCESS POINT IN A WIRELESS LAN - A wireless access device in a local area network (LAN) having a plurality of transceivers. Each transceiver has a directional antenna positioned in a substantially circular array to communicate signals with a plurality of stations in a corresponding sector. Each sector defines a portion of a coverage area surrounding the wireless access device. The wireless access device has a network interface to a data network, and an array controller to control communication of data between the stations and the transceivers, and between the transceivers and the network interface. | 01-22-2009 |
20120230307 | ACCESS POINT IN A WIRELESS LAN - A wireless access device in a local area network (LAN) having a plurality of transceivers. Each transceiver has a directional antenna positioned in a substantially circular array to communicate signals with a plurality of stations in a corresponding sector. Each sector defines a portion of a coverage area surrounding the wireless access device. The wireless access device has a network interface to a data network, and an array controller to control communication of data between the stations and the transceivers, and between the transceivers and the network interface. | 09-13-2012 |
20130121327 | WIRELESS LAN ARRAY - A wireless access device in a local area network (LAN) having a plurality of transceivers. Each transceiver has a directional antenna positioned in a substantially circular array to communicate signals with a plurality of stations in a corresponding sector. Each sector defines a portion of a coverage area surrounding the wireless access device. The wireless access device has a network interface to a data network, and an array controller to control communication of data between the stations and the transceivers, and between the transceivers and the network interface. The array controller is configured to modify channel assignments so as to minimize channel interference dynamically. | 05-16-2013 |
20130121328 | WIRELESS ACCESS POINT ARRAY - A system of at least one wireless access device in a local area network (LAN) having a plurality of transceivers. Each transceiver has a directional antenna positioned in a substantially circular array to communicate signals with a plurality of stations in a corresponding sector. Each sector defines a portion of a coverage area surrounding the wireless access device. The wireless access device has a network interface to a data network, and an array controller to control communication of data between the stations and the transceivers, and between the transceivers and the network interface. The array controller is configured to modify channel assignments so as to minimize channel interference dynamically. | 05-16-2013 |
Kurt Karl Sauter, Thousand Oaks, CA US
Patent application number | Description | Published |
---|---|---|
20150105087 | SYSTEM AND METHOD FOR CONDUCTING WIRELESS SITE SURVEYS - A method for surveying a site for installation of wireless access points is provided. A map of the site under survey is displayed. User input relating to the position of a first wireless device at the site is received. User input relating to the position of a second wireless device at the site is also received. Wireless signals broadcast by the second wireless device are measured using the first wireless device to obtain signal strength values corresponding to the strength of the wireless signals. Attenuation values based on the signal strength values are calculated and assigned to features on the map of the site under survey. | 04-16-2015 |
Mark J. Sauter, Palatine, IL US
Patent application number | Description | Published |
---|---|---|
20110192101 | INTEGRAL WALL BASE AND FLASH COVE - An integral wall base and flash cove having a wall portion, an elongated toe and a concave cove interconnecting the wall portion and the elongated toe in smooth transition. The integral wall base and flash cove can be wrapped around inside and outside corners without the need for a separate molded corner. The integral wall base and flash cove can be installed without required a cove stick or top cap moulding. | 08-11-2011 |
Ryan Patrick Sauter, La Crosse, WI US
Patent application number | Description | Published |
---|---|---|
20120024728 | Free-Standing Instrument Vitrine - A free-standing vitrine for storing instruments is disclosed. The vitrine comprises a transparent portion through which an instrument stored inside the vitrine is viewable when the lid of the vitrine is closed. Furthermore, versions of the free-standing vitrine may be inclined relative to the surface on which the vitrine rests. | 02-02-2012 |
Susan M. Sauter, Murphy, TX US
Patent application number | Description | Published |
---|---|---|
20100220631 | Method for Bring-Up of Voice Over Internet Protocol Telephones - A system and method for implementing telephony devices in a distributed network environment is disclosed. The present invention provides for voice transmissions to be given a dedicated virtual local area network (“VLAN”) for packet transmission and reception to prevent poor quality of service. Non-voice data packets are transmitted on a separate VLAN. | 09-02-2010 |
Susan Marie Sauter, Murphy, TX US
Patent application number | Description | Published |
---|---|---|
20110064003 | CROSS CLUSTER EXTENSION MOBILITY IN INTERNET-PROTOCOL TELEPHONY - In certain embodiments, a system comprises a connection to a network and an application server providing a cross cluster extension mobility (CCEM) service configured to receive a request from a user to log into the CCEM service from a telephony device connected to the network, prompt the user via the telephony device to provide a user ID, determine whether the user is logging in from a home cluster or a remote cluster, and perform a local extension mobility login for the user. | 03-17-2011 |
Tim Sauter, Santa Barbara, CA US
Patent application number | Description | Published |
---|---|---|
20100180356 | Nanoindenter - A new type of indenter is described. This device combines certain sensing and structural elements of atomic force microscopy with a module designed for the use of indentation probes, conventional diamond and otherwise, as well as unconventional designs, to produce high resolution and otherwise superior indentation measurements. | 07-15-2010 |
20120272411 | Nanoindenter - A new type of indenter is described. This device combines certain sensing and structural elements of atomic force microscopy with a module designed for the use of indentation probes, conventional diamond and otherwise, as well as unconventional designs, to produce high resolution and otherwise superior indentation measurements. | 10-25-2012 |
Tom Sauter, Seattle, WA US
Patent application number | Description | Published |
---|---|---|
20110085774 | FIBER OPTIC ADAPTER PLATES WITH INTEGRATED FIBER OPTIC ADAPTERS - Structures, devices and methods are provided for creating fiber optic adapter plates with integrated fiber optic adapters. In one aspect, fiber optic adapter plates having integrated fiber optic adapter subassemblies are formed from a moldable plastic. For example, a molded plastic fiber optic adapter plate can include a molded plastic adapter back plate having a plurality of integrated fiber optic adapter subassemblies and one or more attachment mechanisms that facilitate locating and attaching an adapter front plate having a corresponding plurality of integrated fiber optic adapter subassemblies on the adapter front plate. Advantages provided by integrating fiber optic adapters into the molded plastic assemblies include superior mechanical strength, manufacturing cost reductions and adapter placement flexibility among other advantages. | 04-14-2011 |
Wolfgang Sauter, Burke, VT US
Patent application number | Description | Published |
---|---|---|
20160043048 | PREVENTING MISSHAPED SOLDER BALLS - “Thick line dies” that, during manufacture, avoid locating an upstanding edge of a photoresist layer (for example, the edge of a dry film photoresist layer) on top of a “discontinuity.” In this way solder does not flow into the mechanical interface between the photoresist layer and the layer under the photoresist layer in the vicinity of an upstanding edge of the photoresist layer. | 02-11-2016 |
Wolfgang Sauter, Eagle-Vail, CO US
Patent application number | Description | Published |
---|---|---|
20140339699 | UNDER BALL METALLURGY (UBM) FOR IMPROVED ELECTROMIGRATION - An interconnect structure that includes a substrate having an electrical component present therein, and a under-bump metallurgy (UBM) stack that is present in contact with a contact pad to the electrical component that is present in the substrate. The UBM stack includes a metallic adhesion layer that is direct contact with the contact pad to the electrical component, a copper (Cu) seed layer that is in direct contact with the metallic adhesion layer layer, a first nickel (Ni) barrier layer that is present in direct contact with copper (Cu) seed layer, and a layered structure of at least one copper (Cu) conductor layer and at least one second nickel (Ni) barrier layer present on the first nickel (Ni) barrier layer. A solder ball may be present on second nickel (Ni) barrier layer. | 11-20-2014 |
20150021793 | SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURE - Wire-bonded semiconductor structures using organic insulating material and methods of manufacture are disclosed. The method includes forming a metal wiring layer in an organic insulator layer. The method further includes forming a protective layer over the organic insulator layer. The method further includes forming a via in the organic insulator layer over the metal wiring layer. The method further includes depositing a metal layer in the via and on the protective layer. The method further includes patterning the metal layer with an etch chemistry that is damaging to the organic insulator layer. | 01-22-2015 |
20150041977 | STRUCTURES AND METHODS FOR IMPROVING SOLDER BUMP CONNECTIONS IN SEMICONDUCTOR DEVICES - Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a via formed in a dielectric layer to expose a contact pad and a capture pad formed in the via and over the dielectric layer. The capture pad has openings over the dielectric layer to form segmented features. The solder bump is deposited on the capture pad and the openings over the dielectric layer. | 02-12-2015 |
20150048502 | PREVENTING MISSHAPED SOLDER BALLS - “Thick line dies” that, during manufacture, avoid locating an upstanding edge of a photoresist layer (for example, the edge of a dry film photoresist layer) on top of a “discontinuity.” In this way solder does not flow into the mechanical interface between the photoresist layer and the layer under the photoresist layer in the vicinity of an upstanding edge of the photoresist layer. | 02-19-2015 |
20150333025 | ORGANIC COATING TO INHIBIT SOLDER WETTING ON PILLAR SIDEWALLS - The present invention relates generally to and more particularly, to a method of fabricating a pillar interconnect structure with non-wettable sidewalls and the resulting structure. More specifically, the present invention may include exposing only the sidewalls of a pillar to an organic material that reacts with metal of the pillar to form an organo-metallic layer on sidewalls of the pillar. The organo-metallic layer may prevent solder from wetting on the sidewalls of the pillar during subsequent bonding/reflow processes. | 11-19-2015 |
Wolfgang Sauter, Hinesburg, VT US
Patent application number | Description | Published |
---|---|---|
20110298095 | PASSIVATION LAYER EXTENSION TO CHIP EDGE - Embodiments of the invention provide a semiconductor chip having a passivation layer extending along a surface of a semiconductor substrate to an edge of the semiconductor substrate, and methods for their formation. One aspect of the invention provides a semiconductor chip comprising: a semiconductor substrate; a passivation layer including a photosensitive polyimide disposed along a surface of the semiconductor substrate and extending to at least one edge of the semiconductor substrate; and a channel extending through the passivation layer to the surface of the semiconductor substrate. | 12-08-2011 |
20120119362 | NI PLATING OF A BLM EDGE FOR PB-FREE C4 UNDERCUT CONTROL - A structure and a method of manufacturing a Pb-free Controlled Collapse Chip Connection (C4) with a Ball Limiting Metallurgy (BLM) structure for semiconductor chip packaging that reduce chip-level cracking during the Back End of Line (BEOL) processes of chip-join cool-down. An edge of the BLM structure that is subject to tensile stress during chip-join cool down is protected from undercut of a metal seed layer, caused by wet etch of the chip to remove metal layers from the chip's surface and solder reflow, by an electroplated barrier layer, which covers a corresponding edge of the metal seed layer. | 05-17-2012 |
20120139113 | UNDERCUT-REPAIR OF BARRIER LAYER METALLURGY FOR SOLDER BUMPS AND METHODS THEREOF - A method of making a semiconductor structure includes patterning a barrier layer metallurgy (BLM) which forms an undercut beneath a solder material, and forming a repair material in the undercut and on the solder material. The method also includes removing the repair material from the solder material, and reflowing the solder material. | 06-07-2012 |
20120146212 | SOLDER BUMP CONNECTIONS - Solder bump connections and methods for fabricating solder bump connections. The method includes forming a layer stack containing first and second conductive layers, forming a dielectric passivation layer on a top surface of the second conductive layer, and forming a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer. The method further includes forming a conductive plug in the via opening. The solder bump connection includes first and second conductive layers comprised of different conductors, a dielectric passivation layer on a top surface of the second conductive layer, a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer, and a conductive plug in the via opening. | 06-14-2012 |
20120168956 | CONTROLLING DENSITY OF PARTICLES WITHIN UNDERFILL SURROUNDING SOLDER BUMP CONTACTS - A method forms an integrated circuit structure, using a manufacturing device, to have kerf regions and external contacts, and to have conductive structures in the kerf regions. The method also forms an underfill material on a surface of the integrated circuit structure, using the manufacturing device, that contacts the kerf regions and the external contacts. The underfill material comprises electrically attracted filler particles that affect the coefficient of thermal expansion and elastic modulus of the underfill material. When forming the underfill material, the method applies an electrical charge to the conductive structures and the external contacts. | 07-05-2012 |
20120217636 | Ni PLATING OF A BLM EDGE FOR Pb-FREE C4 UNDERCUT CONTROL - A structure and a method of manufacturing a Pb-free Controlled Collapse Chip Connection (C4) with a Ball Limiting Metallurgy (BLM) structure for semiconductor chip packaging that reduce chip-level cracking during the Back End of Line (BEOL) processes of chip-join cool-down. An edge of the BLM structure that is subject to tensile stress during chip-join cool down is protected from undercut of a metal seed layer, caused by wet etch of the chip to remove metal layers from the chip's surface and solder reflow, by an electroplated barrier layer, which covers a corresponding edge of the metal seed layer. | 08-30-2012 |
20120241916 | WAFER EDGE CONDITIONING FOR THINNED WAFERS - The present invention relates to a method for minimizing breakage of wafers during or after a wafer thinning process. A method of forming a rounded edge to the portion of a wafer remaining after surface grinding process is provided. The method comprises providing a semiconductor wafer having an edge and forming a recess in the edge of the wafer using any suitable mechanical or chemical process. The method further comprises forming a substantially continuous curved shape for at least the edge of the wafer located above the recess. Advantageously, the shape of the wafer is formed prior to the backside grind process to prevent problems caused by the otherwise presence of a sharp edge during the backside grind process. | 09-27-2012 |
20120248604 | SELECTIVE ELECTROMIGRATION IMPROVEMENT FOR HIGH CURRENT C4S - The invention includes embodiments of a method for designing a flip chip and the resulting structure. The starting point is a flip chip with a semiconductor substrate, one or more wiring levels, and a plurality of I/O contact pads (last metal pads/bond pads) for receiving and sending electrical current. There is also a plurality of C4 bumps for connecting the I/O contact pads to another substrate. Then it is determined which of the C4s of the plurality of C4 bumps have a level of susceptibility to electromigration damage that meets or exceeds a threshold level of susceptibility, and in response, plating a conductive structure with a high electrical current carrying capacity (such as a copper pillar, copper pedestal, or partial copper pedestal) onto the corresponding I/O contact pads and adding a solder ball to a top portion of the conductive structure. The resulting structure is a flip chip wherein only a select few C4 bumps use enhanced C4s (such as copper pedestals) reducing the chance of defects. | 10-04-2012 |
20120280399 | BUFFER PAD IN SOLDER BUMP CONNECTIONS AND METHODS OF MANUFACTURE - Structures are provided with raised buffer pads for solder bumps. Methods are also provided for forming the raised buffer pads for solder bumps. The method includes forming a raised localized buffer pad structure on a tensile side of a last metal layer of a solder bump connection. The raised localized buffer pad structure increases a height of a portion of a pad structure of the solder bump connection with respect to a compressive side of the last metal layer. | 11-08-2012 |
20130119534 | METAL PAD STRUCTURE FOR THICKNESS ENHANCEMENT OF POLYMER USED IN ELECTRICAL INTERCONNECTION OF SEMICONDUCTOR DIE TO SEMICONDUCTOR CHIP PACKAGE SUBSTRATE WITH SOLDER BUMP - A topographical feature is formed proximate to a conductive bond pad that is used to couple a solder bump to a semiconductor die. The topographical feature is separated from the conductive bond pad by a gap. In one embodiment, the topographical feature is formed at a location that is slightly beyond the perimeter of the solder bump, wherein an edge of the bump is aligned vertically to coincide with the gap separating the conductive bond pad from the topographical feature. The topographical feature provides thickness enhancement of a non-conductive layer disposed over the semiconductor die and the conductive bond pad and stress buffering. | 05-16-2013 |
20130140695 | SOLDER BUMP CONNECTIONS - Solder bump connections and methods for fabricating solder bump connections. The method includes forming a layer stack containing first and second conductive layers, forming a dielectric passivation layer on a top surface of the second conductive layer, and forming a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer. The method further includes forming a conductive plug in the via opening. The solder bump connection includes first and second conductive layers comprised of different conductors, a dielectric passivation layer on a top surface of the second conductive layer, a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer, and a conductive plug in the via opening. | 06-06-2013 |
20130161822 | CONTROLLING DENSITY OF PARTICLES WITHIN UNDERFILL SURROUNDING SOLDER BUMP CONTACTS - A method forms an integrated circuit structure, using a manufacturing device, to have kerf regions and external contacts, and to have conductive structures in the kerf regions. The method also forms an underfill material on a surface of the integrated circuit structure, using the manufacturing device, that contacts the kerf regions and the external contacts. The underfill material comprises electrically attracted filler particles that affect the coefficient of thermal expansion and elastic modulus of the underfill material. When forming the underfill material, the method applies an electrical charge to the conductive structures and the external contacts. | 06-27-2013 |
20130234315 | STRUCTURES AND METHODS FOR DETECTING SOLDER WETTING OF PEDESTAL SIDEWALLS - Structures and methods for detecting solder wetting of pedestal sidewalls. The structure includes a semiconductor wafer having an array of integrated circuit chips, each of the integrated circuit chips having an array of chip pedestals having respective chip solder columns on top of the chip pedestals, the pedestals spaced apart a first distance in a first direction and a spaced apart second distance in second direction perpendicular to the first direction; and at least one monitor structure disposed in different regions of the wafer from the integrated circuit chips, the monitor structure comprising at least a first pedestal and a first solder column on a top surface of the first pedestal and a second pedestal and a second solder column on a top surface of the second pedestal, the first and the second pedestals spaced apart a third distance, the third distance less than the first and the second distances. | 09-12-2013 |
20130234316 | SELF-ALIGNED POLYMER PASSIVATION/ALUMINUM PAD - The invention provides a semiconductor chip structure having at least one aluminum pad structure and a polyimide buffering layer under the aluminum pad structure, wherein the polyimide buffering layer is self-aligned to the aluminum pad structure, and a method of forming the same. The method includes forming a polyimide buffering layer on a substrate, forming an aluminum pad structure on the buffering layer, and, using the aluminum pad structure as a mask, etching the substrate to remove the polyimide buffering layer from the substrate everywhere except under the aluminum pad structure. | 09-12-2013 |
20130269974 | SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURE - Wire-bonded semiconductor structures using organic insulating material and methods of manufacture are disclosed. The method includes forming a metal wiring layer in an organic insulator layer. The method further includes forming a protective layer over the organic insulator layer. The method further includes forming a via in the organic insulator layer over the metal wiring layer. The method further includes depositing a metal layer in the via and on the protective layer. The method further includes patterning the metal layer with an etch chemistry that is damaging to the organic insulator layer. | 10-17-2013 |
20130320521 | RELEASABLE BURIED LAYER FOR 3-D FABRICATION AND METHODS OF MANUFACTURING - A releasable buried layer for 3-D fabrication and methods of manufacturing is disclosed. The method includes forming an interposer structure which includes forming a carbon rich dielectric releasable layer over a wafer. The method further includes forming back end of the line (BEOL) layers over the carbon rich dielectric layer, including wiring layers and solder bumps. The method further includes bonding the solder bumps to a substrate using flip chip processes. The flip chip processes comprises reflowing the solder bumps and rapidly cooling down the solder bumps which releases the carbon rich dielectric releasable layer from the wafer. | 12-05-2013 |
20140021600 | REDISTRIBUTION LAYER (RDL) WITH VARIABLE OFFSET BUMPS - An integrated circuit (IC) chip is disclosed including a plurality of metal vertical interconnect accesses (vias) in a back end of line (BEOL) layer, a redistribution layer (RDL) on the BEOL layer, the BEOL layer having a plurality of bond pads, each bond pad connected to at least one corresponding metal via through the RDL; and a solder bump connected to each bond pad, wherein each solder bump is laterally offset from the corresponding metal via connected to the bond pad towards a center of the IC chip by an offset distance, wherein the offset distance is non-uniform across the IC chip. In one embodiment, the offset distance for each solder bump is proportionate to a distance between the center of the IC chip and the center of the corresponding solder bump pad structure for that solder bump. | 01-23-2014 |
20140021606 | CONTROL OF SILVER IN C4 METALLURGY WITH PLATING PROCESS - A solder structure for joining an IC chip to a package substrate, and method of forming the same are disclosed. In an embodiment, a structure is formed which includes a wafer having a plurality of solder structures disposed above the wafer. A ball limiting metallurgy (BLM) layer disposed beneath each of the solder structures, above the wafer. At least one of the plurality of solder structures has a first composition, and at least another of the plurality of solder structures has a second composition. | 01-23-2014 |
20140021607 | SOLDER VOLUME COMPENSATION WITH C4 PROCESS - An integrated circuit (IC) chip including solder structures for connection to a package substrate, an IC chip package, and a method of forming the same are disclosed. In an embodiment, an IC chip is provided comprising a wafer having a plurality of solder structures disposed above the wafer. A ball limiting metallurgy (BLM) layer is disposed between each of the plurality of solder structures and the wafer. At least one of the plurality of solder structures has a first diameter and a first height, and at least one other solder structure has a second diameter and a second height. The differing heights and volumes of solder structures facilitate solder volume compensation for chip join improvement on the IC chip side rather than the package side. | 01-23-2014 |
20140061933 | WIRE BOND SPLASH CONTAINMENT - A splash containment structure for semiconductor structures and associated methods of manufacture are provided. A method includes: forming wire bond pads in an integrated circuit chip and forming at least one passivation layer on the chip. The at least one passivation layer includes first areas having a first thickness and second areas having a second thickness. The second thickness is greater than the first thickness. The first areas having the first thickness extend over a majority of the chip. The second areas having the second thickness are adjacent the wire bond pads. | 03-06-2014 |
20140077383 | STRUCTURE AND METHOD OF MAKING AN OFFSET-TRENCH CRACKSTOP THAT FORMS AN AIR GAP ADJACENT TO A PASSIVATED METAL CRACKSTOP - A structure and method of making an offset-trench crackstop, which forms an air gap in a passivation layer that is adjacent to a passivated top metal layer of a metal crackstop in an integrated circuit (IC) die. The offset-trench crackstop may expose a portion of a topmost dielectric layer in the crackstop region, not expose a topmost patterned metal layer of the metal crackstop, and may be interposed between the metal crackstop and an active device region. Alternatively, the offset-trench crackstop may expose a portion of the topmost dielectric layer, which separates an outermost metal layer and an innermost metal layer of the metal crackstop, and does not expose any of the topmost patterned metal layer of the metal crackstop, where the innermost metal layer of the metal crackstop is interposed between the offset-trench crackstop in the crackstop region and the active device region of the IC die. | 03-20-2014 |
20140084453 | OVERCOMING CHIP WARPING TO ENHANCE WETTING OF SOLDER BUMPS AND FLIP CHIP ATTACHES IN A FLIP CHIP PACKAGE - Structures and methods for forming good electrical connections between an integrated circuit (IC) chip and a chip carrier of a flip chip package include forming one of: a tensile layer on a front side of the IC chip, which faces a tops surface of the chip carrier, and a compressive layer on the backside of the IC chip. Addition of one of: a tensile layer to the front side of the IC chip and a compressive layer the backside of the IC chip, may reduce or modulate warpage of the IC chip and enhance wetting of opposing solder surfaces of solder bumps on the IC chip and solder formed on flip chip (FC) attaches of a chip carrier during making of the flip chip package. | 03-27-2014 |
20140097524 | COPLANAR WAVEGUIDE FOR STACKED MULTI-CHIP SYSTEMS - An approach for a coplanar waveguide structure in stacked multi-chip systems is provided. A method of manufacturing a semiconductor structure includes forming a first coplanar waveguide in a first chip. The method also includes forming a second coplanar waveguide in a second chip. The method further includes directly connecting the first coplanar waveguide to the second coplanar waveguide using a plurality of chip-to-chip connections. | 04-10-2014 |
20140117535 | COMPENSATING FOR WARPAGE OF A FLIP CHIP PACKAGE BY VARYING HEIGHTS OF A REDISTRIBUTION LAYER ON AN INTEGRATED CIRCUIT CHIP - Structures and methods of making a flip chip package that employ polyimide pads of varying heights at a radial distance from a center of an integrated circuit (IC) chip for a flip chip package. The polyimide pads may be formed under electrical connectors, which connect the IC chip to a chip carrier of the flip chip package, so that electrical connectors formed on polyimide pads of greater height are disposed at a greater radial distance from the center of the IC chip, while electrical connectors formed on polyimide pads of a lesser height are disposed more proximately to the center of the IC chip. Electrical connectors of a greater relative height to the IC chip's surface may compensate for a gap, produced by heat-induced warpage during the making of the flip chip package, that separates the electrical connectors on the IC chip from flip chip attaches on the chip carrier. | 05-01-2014 |
20140246757 | THERMALLY-OPTIMIZED METAL FILL FOR STACKED CHIP SYSTEMS - Stacked chip systems and design structures for stacked chip systems, as well as methods and computer program products for placing thermal conduction paths in a stacked chip system. The method may include determining an availability of space in a layout of an interconnect structure of a first chip for a fill shape structure extending partially through the interconnect structure to thermally couple a metal feature in the interconnect structure with a bonding layer between the interconnect structure of the first chip and a second chip. If space is available, the fill shape structure may be placed in the layout of the interconnect structure of the first chip. The stacked chip system may include the first and second chips, the bonding layer between the interconnect structure of the first chip and the second chip, and the fill shape structure. | 09-04-2014 |
20140264741 | CAPACITOR USING BARRIER LAYER METALLURGY - A metal-insulator-metal (MIM) capacitor using barrier layer metallurgy and methods of manufacture are disclosed. The method includes forming a bottom plate of a metal-insulator-metal (MIM) capacitor and a bonding pad using a single masking process. The method further includes forming a MIM dielectric on the bottom plate. The method further includes forming a top plate of the MIM capacitor on the MIM dielectric. The method further includes forming a solder connection on the bonding pad. | 09-18-2014 |
20140266292 | SEMICONDUCTOR TEST WAFER AND METHODS FOR USE THEREOF - A test wafer is disclosed with a first side configured to have integrated circuits formed thereon and a second side with a test structure formed thereon. The test wafer can include electrical test structures embedded in the second side of the wafer. An electrical test of the test wafer can be performed after handling by a tool used in a wafer manufacturing process to determine if the tool caused a defect on the second side of the wafer. The test structure can include a blanket layer disposed on the second side of the wafer. The test wafer can then be exposed to a wet etch and inspected thereafter for the presence of an ingress path caused from the etch chemistry. The presence of an ingress path is an indication that the tool used prior to the wet etch caused a defect in the wafer. | 09-18-2014 |
20140319522 | FAR BACK END OF THE LINE METALLIZATION METHOD AND STRUCTURES - Disclosed are a method for metallization during semiconductor wafer processing and the resulting structures. In this method, a passivation layer is patterned with first openings aligned above and extending vertically to metal structures below. A mask layer is formed and patterned with second openings aligned above the first openings, thereby forming two-tier openings extending vertically through the mask layer and passivation layer to the metal structures below. An electrodeposition process forms, in the two-tier openings, both under-bump pad(s) and additional metal feature(s), which are different from the under-bump pad(s) (e.g., a wirebond pad; a final vertical section of a crackstop structure; and/or a probe pad). Each under-bump pad and additional metal feature initially comprises copper with metal cap layers thereon. The mask layer is removed, an additional mask layer is formed and patterned with third opening(s) exposing only the under-bump pad(s) and solder material is deposited on the under-bump pad(s). | 10-30-2014 |
20150044864 | COMPENSATING FOR WARPAGE OF A FLIP CHIP PACKAGE BY VARYING HEIGHTS OF A REDISTRIBUTION LAYER ON AN INTEGRATED CIRCUIT CHIP - Structures and methods of making a flip chip package that employ polyimide pads of varying heights at a radial distance from a center of an integrated circuit (IC) chip for a flip chip package. The polyimide pads may be formed under electrical connectors, which connect the IC chip to a chip carrier of the flip chip package, so that electrical connectors formed on polyimide pads of greater height are disposed at a greater radial distance from the center of the IC chip, while electrical connectors formed on polyimide pads of a lesser height are disposed more proximately to the center of the IC chip. Electrical connectors of a greater relative height to the IC chip's surface may compensate for a gap, produced by heat-induced warpage during the making of the flip chip package, that separates the electrical connectors on the IC chip from flip chip attaches on the chip carrier. | 02-12-2015 |
Wolfgang Sauter, Avon, CO US
Patent application number | Description | Published |
---|---|---|
20140077367 | SOLDER INTERCONNECT WITH NON-WETTABLE SIDEWALL PILLARS AND METHODS OF MANUFACTURE - A solder interconnect structure is provided with non-wettable sidewalls and methods of manufacturing the same. The method includes forming a nickel or nickel alloy pillar on an underlying surface. The method further includes modifying the sidewall of the nickel or nickel alloy pillar to prevent solder wetting on the sidewall. | 03-20-2014 |
20150097283 | PLUG VIA FORMATION WITH GRID FEATURES IN THE PASSIVATION LAYER - Solder bump connections and methods for fabricating solder bump connections. A passivation layer is formed on a dielectric layer. Via openings extend through the passivation layer from a top surface of the passivation layer to a metal line in the passivation layer. A conductive layer is formed on the top surface of the passivation layer and within each via opening. When the passivation layer and the conductive layer are planarized, a plug is formed that includes sections in the via openings. Each section is coupled with the metal line. | 04-09-2015 |
Wolfgang Sauter, Charlotte, VT US
Patent application number | Description | Published |
---|---|---|
20090189286 | FINE PITCH SOLDER BUMP STRUCTURE WITH BUILT-IN STRESS BUFFER - A fine pitch solder bump structure with a built-in stress buffer that is utilized in electronic packages, and a method of producing the fine pitch solder bump structure with built-in stress buffer. Employed is a very thick final passivation layer that is constituted of a polyimide as a so-called “cushion” for a minimal thickness of UBM (BLM) pad and solder material, while concurrently completely separating the resultingly produced polyimide islands, so that the polyimide material provides most of the physical height for the “standoff” of a modified C4 (controlled collapse chip connection) structure. In employing the polyimide material as the primary structural component of the vertical chip package interconnect in this particular inventive manner, the inherent stress buffering property of the polyimide material is utilized to full advantage by effectively reducing the high stresses encountered during chip manufacture processing steps, such as chip join, reflow, preconditioning and reliability thermal cycle stressing. | 07-30-2009 |
20120061832 | COLLAR STRUCTURE AROUND SOLDER BALLS THAT CONNECT SEMICONDUCTOR DIE TO SEMICONDUCTOR CHIP PACKAGE SUBSTRATE - In one embodiment, a collar structure includes a non-conductive layer that relieves stress around the perimeter of each of the solder balls that connect the semiconductor die to the semiconductor chip package substrate, and another non-conductive layer placed underneath to passivate the entire surface of the die. | 03-15-2012 |
Wolfgang Sauter, Vail, CO US
Patent application number | Description | Published |
---|---|---|
20150311170 | CONTACT AND SOLDER BALL INTERCONNECT - A semiconductor device fabrication method includes forming a barrier layer upon a dielectric layer, forming a pillar interconnect structure upon the barrier layer, forming solder upon the pillar interconnect structure, reflowing the solder to release solder voids, forming a perimeter material around at least a portion of an exposed sidewall of the pillar, and removing the barrier layer exterior to the pillar interconnect structure. Another fabrication method includes forming the barrier layer, forming the pillar interconnect structure, forming the solder upon the pillar interconnect structure, forming a perimeter material on exposed surfaces of the pillar interconnect structure, and removing the barrier layer on the surface of the dielectric layer exterior to the pillar interconnect structure. Another fabrication method includes forming the barrier layer, forming the pillar interconnect structure, forming a wettable material on sidewalls of the pillar, and removing the barrier layer exterior to the pillar interconnect structure. | 10-29-2015 |
Wolfgang Sauter, Essex Junction, VT US
Patent application number | Description | Published |
---|---|---|
20110012249 | IC CHIP PACKAGE HAVING IC CHIP WITH OVERHANG AND/OR BGA BLOCKING UNDERFILL MATERIAL FLOW AND RELATED METHODS - An IC chip package, in one embodiment, may include an IC chip including an upper surface including an overhang extending beyond a sidewall of the IC chip, and underfill material about the sidewall and under the overhang. The overhang prevents underfill material from extending over an upper surface of the IC chip. In another embodiment, a ball grid array (BGA) is first mounted to landing pads on a lower of two joined IC chip packages. Since the BGA is formed on the lower IC chip package first, the BGA acts as a dam for the underfill material thereon. The underfill material extends about the respective IC chip and surrounds a bottom portion of a plurality of solder elements of the BGA and at least a portion of respective landing pads thereof. | 01-20-2011 |
20110193218 | Solder Interconnect with Non-Wettable Sidewall Pillars and Methods of Manufacture - A solder interconnect structure is provided with non-wettable sidewalls and methods of manufacturing the same. The method includes forming a nickel or nickel alloy pillar on an underlying surface. The method further includes modifying the sidewall of the nickel or nickel alloy pillar to prevent solder wetting on the sidewall. | 08-11-2011 |
Wolfgang W. Sauter, Hinesburg, VT US
Patent application number | Description | Published |
---|---|---|
20150037971 | CHIP CONNECTION STRUCTURE AND METHOD OF FORMING - Chip connection structures and related methods of forming such structures are disclosed. In one case, an interconnect structure is disclosed, the structure including: a pillar connecting an integrated circuit chip and a substrate, the pillar including a barrier layer, a first copper layer over the barrier layer, and a first solder layer over the first copper layer. | 02-05-2015 |