Patent application number | Description | Published |
20080265944 | Output Buffer Circuit and Differential Output Buffer Circuit, and Transmission Method - In an output buffer circuit including Inverter | 10-30-2008 |
20090003463 | OUTPUT BUFFER CIRCUIT, SIGNAL TRANSMISSION INTERFACE CIRCUIT AND APPARATUS - An output buffer circuit which transmits a logic signal to a transmission line includes a transmission pre-emphasis output circuit and a transmission pre-emphasis amount determination circuit. The transmission pre-emphasis output circuit controls a pre-emphasis amount according to an output signal from the transmission pre-emphasis amount determination circuit. The transmission pre-emphasis amount determination circuit adjusts a pre-emphasis amount and the number of pre-emphasis taps according to a pseudo loss control signal, controls a pre-emphasis amount of a transmission signal so that a signal amplitude is made smaller in a signal component with a high frequency than that of a signal component with a low frequency, and imparts signal degradation to a received waveform to realize transmission loss in a pseudo manner. | 01-01-2009 |
20100219856 | OUTPUT BUFFER CIRCUIT AND DIFFERENTIAL OUTPUT BUFFER CIRCUIT, AND TRANSMISSION METHOD - In an output buffer circuit including Inverter | 09-02-2010 |
20110007487 | LSI PACKAGE, PRINTED BOARD AND ELECTRONIC DEVICE - A technology capable of reducing a crosstalk noise generated between through holes of an LSI package and a printed board at low cost is provided. In an electronic device in which an LSI package is mounted on a printed board, a plurality of transmission terminals and a plurality of reception terminals are provided, and the plurality of transmission terminals include transmission terminal pairs which transmit a differential signal and the plurality of reception terminals include reception terminal pairs which receive the differential signal. In the LSI package, two transmission terminal pairs and two reception terminal pairs are respectively adjacent to each other and are arranged so that a line which connects the terminals of one pair intersects with a line which connects the terminals of the other pair. | 01-13-2011 |
20110215830 | OUTPUT BUFFER CIRCUIT AND DIFFERENTIAL OUTPUT BUFFER CIRCUIT, AND TRANSMISSION METHOD - An output buffer includes inverters, a delay circuit for delaying an input signal, buffers and switches. The output buffer transmits a logic signal to a transmission path and, in accordance with an amount of signal attenuation in the transmission path, creates a waveform including four or more kinds of signal voltages. The buffers are redundantly connected in parallel, and the number of buffers concurrently turn ON is controlled by respective switches provided in series with output resistors of the buffers. By selecting the buffers of switches which are turned ON, the preemphasis amount and a number of preemphasis taps are adjusted through a selector logic selection signal so that the preemphasis amount is made variable and the ON resistance of the buffers is made constant. | 09-08-2011 |
20120112849 | DATA TRANSMISSION SYSTEM AND SEMICONDUCTOR CIRCUIT - A data transmission system is provided in which it is possible to perform both of suppressing the degrading of the slew rate and suppressing the ringing even if load capacitance of an input buffer is changed. | 05-10-2012 |
20120194304 | Equalizer Circuit and Printed Circuit Board - An equalizer circuit includes a passive equalizer having an inductor connected in parallel to a signal interconnection line, the inductor being made up of a conductor portion formed on a side face of a through-hole of a circuit board. | 08-02-2012 |
20120262885 | SIGNAL TRANSFER CIRCUIT - Provided is a signal transfer circuit which uses a low cost circuit board with a high packing density but is capable of reducing a crosstalk noise between signal lines and also reducing a reflection noise due to a stub. A signal transfer circuit of the present invention is configured such that lead terminals of electronic components and through-hole vias are connected to each other by surface wirings, respectively, to allow no branching from the middle of the through-hole vias. Further, first wirings connecting a first electronic component are each arranged between a corresponding pair of second wirings connecting a second electronic component, and signals are transmitted through the first wirings and the second wirings by interleaved transmission. | 10-18-2012 |
20120302075 | Signal Wiring Board and Signal Transmission Circuit - The present invention maintains plugging-unplugging durability of connector pins for connecting to a signal wiring board, as well as reduces a stub length of a through hole connecting to a signal wiring. In the signal wiring board according to the present invention, a through hole connecting to the inner-layer signal wiring is formed to be shorter than the other through holes. A through hole in which a connector pin connecting to the inner-layer signal wiring is inserted is formed to have a length corresponding to a depth of the inner-layer signal wiring. | 11-29-2012 |
20130207234 | SEMICONDUCTOR APPARATUS, SIGNAL TRANSMISSION SYSTEM AND SIGNAL TRANSMISSION METHOD - A slew rate of a signal transmitted between a semiconductor device having a small load capacitance and a semiconductor device having a large load capacitance is improved. When a signal is transmitted to the semiconductor device (for example, a memory device) having the large load capacitance, pre-emphasis is performed, and when a signal is transmitted to the semiconductor device (for example, a memory controller) having the small load capacitance, pre-emphasis is not performed or is slightly performed. By this, when the signal is transmitted to the memory device, blunting in signal rising due to the load capacitance is suppressed, and when the signal is transmitted to the memory controller, ringing due to the reflection of the signal is suppressed, and the slew rate of the data transmission is improved. | 08-15-2013 |
20130307582 | SEMICONDUCTOR DEVICE - To suppress power consumption and enhance signal quality as compared with the case where first and second semiconductor elements are terminated only by on-chip input termination resistor circuits. A first semiconductor element with a switching function and a second semiconductor element with a switching function are connected to each other with a substrate interconnection, and a resistor element is connected in parallel with the substrate interconnection. The resistor element is placed at an arbitrary position or a branch point on the signal interconnection. | 11-21-2013 |
20140112073 | SIGNAL TRANSMISSION SYSTEM AND STORAGE SYSTEM - A signal transmission system is provided which connects a memory controller and a plurality of semiconductor memories. The signal transmission system comprises a semiconductor device arranged between the memory controller and the plurality of memories, in which: the semi-conductor device comprises a control circuit; and the control circuit receives a signal from the semiconductor memory and outputs a control signal to the memory controller in response to the signal from the semiconductor memory. | 04-24-2014 |