Patent application number | Description | Published |
20080253171 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: a memory cell array including a plurality of SRAM memory cells; a characteristic measuring circuit including a plurality of transistor circuits connected in parallel; and a first terminal. The plurality of transistor circuits each include a first transistor configured in the same manner as one of transistors included in one of the SRAM memory cells. The first transistor is connected so as to control current between the first terminal and a node at a reference potential according to a voltage supplied to a gate of the first transistor. | 10-16-2008 |
20090161412 | SEMICONDUCTOR MEMORY - In a semiconductor memory including word lines and bit lines arranged in a matrix and a plurality of memory cells provided at intersections of the word lines and the bit lines, a bit line precharge circuit is provided for controlling the potential of a low-data holding power supply coupled to memory cells provided on a corresponding one of the bit lines. In a write operation, the bit line precharge circuit controls the potential of a low-data holding power supply of a memory cell corresponding to a selected bit line to be higher than the potential of a low-data holding power supply of a memory cell corresponding to an unselected bit line. | 06-25-2009 |
20090201745 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistors | 08-13-2009 |
20100277991 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistors | 11-04-2010 |
20110007575 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit. | 01-13-2011 |
20110188327 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit. | 08-04-2011 |
20110267914 | SEMICONDUCTOR MEMORY DEVICE - Characteristics of both a memory cell and a peripheral circuit are degraded due to random variations, and a defective characteristic occurs in a combination of components having a substantially worst characteristic at a macro level. To solve this problem, a selector is provided between the memory cell and the peripheral circuit so that a positive phase and a negative phase of bit lines are switched at a portion where the defective characteristic occurs. Alternatively, the combination of a bit line and a sense amplifier is switched between adjacent data input/output sections, for example. In other words, the defective characteristic is repaired or corrected by canceling the combination of worst components. | 11-03-2011 |
20130021839 | SEMICONDUCTOR MEMORY - A semiconductor memory includes a plurality of memory cells. The plurality of memory cells each include a latch having two inverters, where an input node and an output node of one of the inverters are respectively coupled to an output node and to an input node of the other one of the inverters, a first switch coupled in series with the latch between a first and a second power sources, and a second switch coupled in parallel with the first switch. | 01-24-2013 |