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Saripalli, US

Ganesh R. Saripalli, San Diego, CA US

Patent application numberDescriptionPublished
20110074615WIDEBAND DIGITAL TO ANALOG CONVERTER WITH BUILT-IN LOAD ATTENUATOR - A circuit for digital-to-analog conversion is described. The circuit includes a digital-to-analog converter (DAC). The DAC includes a double cascaded current source and a differential current-mode switch (DCMS). The circuit further includes a direct current (DC) offset stage. The circuit also includes a load attenuator. The double cascaded current source may be between the DCMS and a rail voltage.03-31-2011

Ramakrishna Saripalli, Cornelius, OR US

Patent application numberDescriptionPublished
20090037614Offloading input/output (I/O) virtualization operations to a processor - In one embodiment, the present invention includes a method for receiving a request for a direct memory access (DMA) operation in an input/output (I/O) hub, where the request includes a device virtual address (DVA) associated with the DMA operation, determining in the I/O hub whether to perform an address translation to translate the DVA into a physical address (PA), and sending the request with the DVA from the I/O hub to a processor coupled to the I/O hub if the I/O hub determines not to perform the address translation. Other embodiments are described and claimed.02-05-2009
20090037624Cache coherent switch device - In one embodiment, the present invention includes a switch device to be coupled between a first semiconductor component and a processor node by interconnects of a communication protocol that provides for cache coherent transactions and non-cache coherent transactions. The switch device includes logic to handle cache coherent transactions from the first semiconductor component to the processor node, while the first semiconductor component does not include such logic. Other embodiments are described and claimed.02-05-2009
20100169673Efficient remapping engine utilization - A device, system, and method are disclosed. In one embodiment device includes remapping engine reallocation logic that is capable of monitoring a first amount of traffic that is translated by a first remapping engine. If the first amount of traffic reaches the threshold level of the first remapping engine, then the logic will divert a portion of the traffic to be translated by a second remapping engine.07-01-2010
20100205380Cache Coherent Switch Device - In one embodiment, the present invention includes a switch device to be coupled between a first semiconductor component and a processor node by interconnects of a communication protocol that provides for cache coherent transactions and non-cache coherent transactions. The switch device includes logic to handle cache coherent transactions from the first semiconductor component to the processor node, while the first semiconductor component does not include such logic. Other embodiments are described and claimed.08-12-2010
20110153956Cache Coherent Switch Device - In one embodiment, the present invention includes a switch device to be coupled between a first semiconductor component and a processor node by interconnects of a communication protocol that provides for cache coherent transactions and non-cache coherent transactions. The switch device includes logic to handle cache coherent transactions from the first semiconductor component to the processor node, while the first semiconductor component does not include such logic. Other embodiments are described and claimed.06-23-2011
20110252168Handling Atomic Operations For A Non-Coherent Device - In one embodiment, the present invention includes a method for receiving a non-coherent atomic request from a device coupled to an agent via a non-coherent link, accessing a mapping table of the agent to convert the non-coherent atomic request into a coherent atomic request, and transmitting the coherent atomic request via a coherent link to a second agent coupled to the agent to cause the second agent to be a completer of the non-coherent atomic request. Other embodiments are described and claimed.10-13-2011
20110302425SYSTEMS, METHODS, AND APPARATUS TO VIRTUALIZE TPM ACCESSES - Embodiments of system, method, and apparatus for virtualizing TPM accesses is described. In some embodiments, an apparatus including a CPU core to execute a software program, a manageability engine coupled to the CPU core, the manageability engine to receive a trusted platform module (TPM) command requested by the software program and to process the TPM command utilizing a manageability firmware by at least creating a TPM network packet, and a network interface coupled to the manageability engine to transmit the TPM network packet to a remote TPM that is external to the apparatus for processing is utilized as a part of this virtualization process.12-08-2011

Patent applications by Ramakrishna Saripalli, Cornelius, OR US

Ramesh Saripalli, Irvine, CA US

Patent application numberDescriptionPublished
20090024776HIGH DATA RATE SERIAL PERIPHERAL INTERFACE - An improved high performance scheme is provided with a serial peripheral interface (SPI) to enable microcontroller-based products and other components and devices to achieve a higher serial transmit and receive data rate.01-22-2009

Ramesh Saripalli, Tucson, AZ US

Patent application numberDescriptionPublished
20080209252PIPELINED CLOCK STRETCHING CIRCUITRY AND METHOD FOR I2C LOGIC SYSTEM - A system for increasing the data throughput of an I2C bus including a serial clock conductor (08-28-2008

Patent applications by Ramesh Saripalli, Tucson, AZ US

Vinay Saripalli, University Park, PA US

Patent application numberDescriptionPublished
20110299326TFET BASED 4T MEMORY DEVICES - A four transistor (4T) memory device is provided. The device includes a first cell transistor and a second cell transistor, the first and second cell transistors coupled to each other and defining latch circuitry having at least one multi-stable node. The device further includes a first access transistor and a second access transistor, the first and second access transistors coupling the at least one multi-stable node to at least one bit-line. In the device, each of the first and second cell transistors and each of the first and second access transistors is a unidirectional field effect transistor configured for conducting current in a first direction and to be insubstantially incapable of conducting current in a second direction.12-08-2011

Yoganand Saripalli, Sunnyvale, CA US

Patent application numberDescriptionPublished
20090269512NONPLANAR FACEPLATE FOR A PLASMA PROCESSING CHAMBER - A method and apparatus for adjust local plasma density during a plasma process. One embodiment provides an electrode assembly comprising a conductive faceplate having a nonplanar surface. The nonplanar surface is configured to face a substrate during processing and the conductive faceplate is disposed so that the nonplanar surface is opposing a substrate support having an electrode. The conductive faceplate and the substrate support form a plasma volume. The nonplanar surface is configured to adjust electric field between the conductive plate and the electrode by varying a distance between the conductive plate and the electrode.10-29-2009

Yoganand N. Saripalli, Santa Clara, CA US

Patent application numberDescriptionPublished
20090093128METHODS FOR HIGH TEMPERATURE DEPOSITION OF AN AMORPHOUS CARBON LAYER - Methods for high temperature deposition an amorphous carbon film with improved step coverage are provided. In one embodiment, a method for of depositing an amorphous carbon film includes providing a substrate in a process chamber, heating the substrate at a temperature greater than 500 degrees Celsius, supplying a gas mixture comprising a hydrocarbon compound and an inert gas into the process chamber containing the heated substrate, and depositing an amorphous carbon film on the heated substrate having a stress of between 100 mega-pascal (MPa) tensile and about 100 mega-pascal (MPa) compressive.04-09-2009