Patent application number | Description | Published |
20090272717 | METHOD AND APPARATUS OF A SUBSTRATE ETCHING SYSTEM AND PROCESS - Embodiments of the invention relate to a substrate etching system and process. In one embodiment, a method may include depositing material on the substrate during a deposition process, etching a first layer of the substrate during a first etch process, and etching a second layer of the substrate during a second etch process, wherein a first bias power is applied to the substrate during the first process, and wherein a second bias power is applied to the substrate during the second etch process. In another embodiment, a system may include a gas delivery system containing a first gas panel for supplying a first gas to a chamber, a second gas panel for supplying a second gas to the chamber, and a plurality of flow controllers for directing the gases to the chamber to facilitate rapid gas transitioning between the gases to and from the chamber and the panels. | 11-05-2009 |
20110073564 | METHOD AND APPARATUS FOR HIGH EFFICIENCY GAS DISSOCIATION IN INDUCTIVE COUPLE PLASMA REACTOR - Embodiments of the present invention relate to method and apparatus for providing processing gases to a process chamber with improved plasma dissociation efficiency. One embodiment of the present invention provides a baffle nozzle assembly comprising an outer body defining an extension volume connected to a processing chamber. A processing gas is flown to the processing chamber through the extension volume which is exposed to power source for plasma generation. | 03-31-2011 |
20110198229 | ELECTROPLATING APPARATUS BASED ON AN ARRAY OF ANODES - The present invention generally relates to apparatus and methods for plating conductive materials on a substrate. One embodiment of the present invention provides an apparatus for plating a conductive material on a substrate. The apparatus comprises a fluid basin configured to retain an electrolyte, a contact ring configured to support the substrate and contact the substrate electrically, and an anode assembly disposed in the fluid basin, wherein the anode assembly comprises a plurality of anode elements arranged in rows. | 08-18-2011 |
20110312157 | WAFER DICING USING FEMTOSECOND-BASED LASER AND PLASMA ETCH - Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask is composed of a layer covering and protecting the integrated circuits. The mask is patterned with a femtosecond-based laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits. | 12-22-2011 |
20120091098 | HIGH EFFICIENCY GAS DISSOCIATION IN INDUCTIVELY COUPLED PLASMA REACTOR WITH IMPROVED UNIFORMITY - Embodiments of the present invention relate to a plasma chamber having a coil assembly which improves plasma uniformity and improves power coupling to the plasma. One embodiment provides a plasma chamber. The plasma chamber includes a chamber body having sidewalls and a lid, wherein the chamber body defines a processing volume. The plasma chamber further includes a coil assembly disposed over the lid configured to generate inductively coupled plasma within the processing volume, wherein the coil assembly comprises two or more horizontal coils arranged in a common horizontal plane. | 04-19-2012 |
20120305184 | DYNAMIC ION RADICAL SIEVE AND ION RADICAL APERTURE FOR AN INDUCTIVELY COUPLED PLASMA (ICP) REACTOR - Embodiments described herein provide apparatus and methods of etching a substrate using an ion etch chamber having a movable aperture. The ion etch chamber has a chamber body enclosing a processing region, a substrate support disposed in the processing region and having a substrate receiving surface, a plasma source disposed at a wall of the chamber body facing the substrate receiving surface, an ion-radical shield disposed between the plasma source and the substrate receiving surface, and a movable aperture member between the ion-radical shield and the substrate receiving surface. The movable aperture member is actuated by a lift assembly comprising a lift ring and lift supports from the lift ring to the aperture member. The ion-radical shield is supported by shield supports disposed through the aperture member. The aperture size, shape, and/or central axis location may be changed using inserts. | 12-06-2012 |
20120305185 | APPARATUS AND METHODS FOR DRY ETCH WITH EDGE, SIDE AND BACK PROTECTION - Embodiments of the present invention generally relate to a method and apparatus for plasma etching substrates and, more specifically, to a method and apparatus with protection for edges, sides and backs of the substrates being processed. Embodiments of the present invention provide an edge protection plate with an aperture smaller in size than a substrate being processed, wherein the edge protection plate may be positioned in close proximity to the substrate in a plasma chamber. The edge protection plate overlaps edges and/or sides on the substrate to provide protection to reflective coatings on the edge, sides, and back of the substrate. | 12-06-2012 |
20120322233 | WATER SOLUBLE MASK FOR SUBSTRATE DICING BY LASER AND PLASMA ETCH - Methods of dicing substrates having a plurality of ICs. A method includes forming a mask comprising a water soluble material layer over the semiconductor substrate. The mask is patterned with a femtosecond laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the substrate between the ICs. The substrate is then etched through the gaps in the patterned mask to singulate the IC and the water soluble material layer washed off. | 12-20-2012 |
20120322234 | IN-SITU DEPOSITED MASK LAYER FOR DEVICE SINGULATION BY LASER SCRIBING AND PLASMA ETCH - Methods of dicing substrates by both laser scribing and plasma etching. A method includes forming an in-situ mask with a plasma etch chamber by accumulating a thickness of plasma deposited polymer to protect IC bump surfaces from a subsequent plasma etch. Second mask materials, such as a water soluble mask material may be utilized along with the plasma deposited polymer. At least some portion of the mask is patterned with a femtosecond laser scribing process to provide a patterned mask with trenches. The patterning exposing regions of the substrate between the ICs in which the substrate is plasma etched to singulate the IC and the water soluble material layer washed off. | 12-20-2012 |
20120322235 | WAFER DICING USING HYBRID GALVANIC LASER SCRIBING PROCESS WITH PLASMA ETCH - Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask is composed of a layer covering and protecting the integrated circuits. The mask is patterned with a galvanic laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits. | 12-20-2012 |
20120322236 | WAFER DICING USING PULSE TRAIN LASER WITH MULTIPLE-PULSE BURSTS AND PLASMA ETCH - Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask is composed of a layer covering and protecting the integrated circuits. The mask is patterned with a pulse train laser scribing process using multiple-pulse bursts to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits. | 12-20-2012 |
20120322237 | LASER AND PLASMA ETCH WAFER DICING USING PHYSICALLY-REMOVABLE MASK - Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask covers and protects the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to form singulated integrated circuits. The patterned mask is then separated from the singulated integrated circuits. | 12-20-2012 |
20120322238 | LASER AND PLASMA ETCH WAFER DICING USING WATER-SOLUBLE DIE ATTACH FILM - Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The semiconductor wafer is disposed on a water-soluble die attach film. The mask covers and protects the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to form singulated integrated circuits. The water-soluble die attach film is then patterned with an aqueous solution. | 12-20-2012 |
20120322239 | HYBRID LASER AND PLASMA ETCH WAFER DICING USING SUBSTRATE CARRIER - Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The semiconductor wafer is supported by a substrate carrier. The mask is then patterned with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits while supported by the substrate carrier. | 12-20-2012 |
20120322241 | MULTI-LAYER MASK FOR SUBSTRATE DICING BY LASER AND PLASMA ETCH - Methods of dicing substrates having a plurality of ICs. A method includes forming a multi-layered mask comprising a first mask material layer soluble in a solvent over the semiconductor substrate and a second mask material layer, insoluble in the solvent, over the first mask material layer. The multi-layered mask is patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the substrate between the ICs. The substrate is then plasma etched through the gaps in the patterned mask to singulate the IC with the second mask material layer protecting the first mask material layer for at least a portion of the plasma etch. The soluble material layer is dissolved subsequent to singulation to remove the multi-layered mask. | 12-20-2012 |
20120322242 | MULTI-STEP AND ASYMMETRICALLY SHAPED LASER BEAM SCRIBING - Methods of dicing substrates by both laser scribing and plasma etching. A method includes laser ablating material layers, the ablating leading with a first irradiance and following with a second irradiance, lower than the first. Multiple passes of a beam adjusted to have different fluence level or multiple laser beams having various fluence levels may be utilized to ablate mask and IC layers to expose a substrate with the first fluence level and then clean off redeposited materials from the trench bottom with the second fluence level. A laser scribe apparatus employing a beam splitter may provide first and second beams of different fluence from a single laser. | 12-20-2012 |
20130000731 | METHOD AND APPARATUS FOR FAST GAS EXCHANGE, FAST GAS SWITCHING, AND PROGRAMMABLE GAS DELIVERY - Embodiments of the invention relate to a gas delivery system. The gas delivery system includes a fast gas exchange module in fluid communication with one or more gas panels and a process chamber. The fast gas exchange module has first and second sets of flow controllers and each of first and second sets of flow controllers has multiple flow controllers. The flow controller is configured such that each of the flow controllers in the first and second sets of the flow controllers is independently operated to selectively open to divert gas to the process chamber or an exhaust. The first and second sets of flow controllers are operated for synchronized switching of gases in a pre-determined timed sequence of flow controller actuation. The invention enables fast switch of resultant gas flow in the process chamber while having individual flow controller operated at lower switching speed to provide longer service life. | 01-03-2013 |
20130017668 | WAFER DICING USING HYBRID SPLIT-BEAM LASER SCRIBING PROCESS WITH PLASMA ETCHAANM Lei; Wei-ShengAACI San JoseAAST CAAACO USAAGP Lei; Wei-Sheng San Jose CA USAANM Eaton; BradAACI Menlo ParkAAST CAAACO USAAGP Eaton; Brad Menlo Park CA USAANM Yalamanchili; Madhava RaoAACI Morgan HillAAST CAAACO USAAGP Yalamanchili; Madhava Rao Morgan Hill CA USAANM Singh; SaravjeetAACI Santa ClaraAAST CAAACO USAAGP Singh; Saravjeet Santa Clara CA USAANM Kumar; AjayAACI CupertinoAAST CAAACO USAAGP Kumar; Ajay Cupertino CA USAANM Iyer; AparnaAACI SunnyvaleAAST CAAACO USAAGP Iyer; Aparna Sunnyvale CA US - Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask is composed of a layer covering and protecting the integrated circuits. The mask is patterned with a split-beam laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits. | 01-17-2013 |
20130267076 | WAFER DICING USING HYBRID MULTI-STEP LASER SCRIBING PROCESS WITH PLASMA ETCH - Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask is composed of a layer covering and protecting the integrated circuits. The mask is patterned with a multi-step laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits. | 10-10-2013 |
20130299088 | LASER AND PLASMA ETCH WAFER DICING USING WATER-SOLUBLE DIE ATTACH FILM - Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The semiconductor wafer is disposed on a water-soluble die attach film. The mask covers and protects the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to form singulated integrated circuits. The water-soluble die attach film is then patterned with an aqueous solution. | 11-14-2013 |
20140015109 | METHOD OF DICED WAFER TRANSPORTATION - Methods of dicing semiconductor wafers, and transporting singulated die, are described. In an example, a method of dicing a wafer having a plurality of integrated circuits thereon involves dicing the wafer into a plurality of singulated dies disposed above a dicing tape. The method also involves forming a water soluble material layer over and between the plurality of singulated dies, above the dicing tape. | 01-16-2014 |
20140017880 | LASER, PLASMA ETCH, AND BACKSIDE GRIND PROCESS FOR WAFER DICING - Front side laser scribing and plasma etch are performed followed by back side grind to singulate integrated circuit chips (ICs). A mask is formed covering ICs formed on the wafer, as well as any bumps providing an interface to the ICs. The mask is patterned by laser scribing to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer, below thin film layers from which the ICs are formed. The semiconductor wafer is then etched through the gaps in the patterned mask to advance a front of an etched trench partially through the semiconductor wafer thickness. The front side mask is removed, a backside grind tape applied to the front side, and a back side grind performed to reach the etched trench, thereby singulating the ICs. | 01-16-2014 |
20140017881 | LASER SCRIBING AND PLASMA ETCH FOR HIGH DIE BREAK STRENGTH AND CLEAN SIDEWALL - In embodiments, a hybrid wafer or substrate dicing process involving an initial laser scribe and subsequent plasma etch is implemented for die singulation. The laser scribe process may be used to cleanly remove a mask layer, organic and inorganic dielectric layers, and device layers. The laser etch process may then be terminated upon exposure of, or partial etch of, the wafer or substrate. In embodiments, a multi-plasma etching approach is employed to dice the wafers where an isotropic etch is employed to improve the die sidewall following an anisotropic etch. The isotropic etch removes anisotropic etch byproducts, roughness, and/or scalloping from the anisotropically etched die sidewalls after die singulation. | 01-16-2014 |
20140065797 | IN-SITU DEPOSITED MASK LAYER FOR DEVICE SINGULATION BY LASER SCRIBING AND PLASMA ETCH - Methods of dicing substrates by both laser scribing and plasma etching. A method includes forming an in-situ mask with a plasma etch chamber by accumulating a thickness of plasma deposited polymer to protect IC bump surfaces from a subsequent plasma etch. Second mask materials, such as a water soluble mask material may be utilized along with the plasma deposited polymer. At least some portion of the mask is patterned with a femtosecond laser scribing process to provide a patterned mask with trenches. The patterning exposing regions of the substrate between the ICs in which the substrate is plasma etched to singulate the IC and the water soluble material layer washed off. | 03-06-2014 |
20140120697 | WAFER DICING USING FEMTOSECOND-BASED LASER AND PLASMA ETCH - Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width. | 05-01-2014 |
20140120698 | WAFER DICING USING HYBRID MULTI-STEP LASER SCRIBING PROCESS WITH PLASMA ETCH - Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask is composed of a layer covering and protecting the integrated circuits. The mask is patterned with a multi-step laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits. | 05-01-2014 |
20140144585 | HYBRID LASER AND PLASMA ETCH WAFER DICING USING SUBSTRATE CARRIER - Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The semiconductor wafer is supported by a substrate carrier. The mask is then patterned with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits while supported by the substrate carrier. | 05-29-2014 |
20140174659 | WATER SOLUBLE MASK FOR SUBSTRATE DICING BY LASER AND PLASMA ETCH - Methods of dicing substrates having a plurality of ICs are disclosed. A method includes forming a mask comprising a water soluble material layer over the semiconductor substrate. The mask is patterned with a femtosecond laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the substrate between the ICs. The substrate is then etched through the gaps in the patterned mask to singulate the IC and the water soluble material layer is washed off. | 06-26-2014 |
20140179084 | WAFER DICING FROM WAFER BACKSIDE - Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. For example, a method includes applying a protection tape to a wafer front side, the wafer having a dicing tape attached to the wafer backside. The dicing tape is removed from the wafer backside to expose a die attach film disposed between the wafer backside and the dicing tape. Alternatively, if no die attach film is initially disposed between the wafer backside and the dicing tape, a die attach film is applied to the wafer backside at this operation. A water soluble mask is applied to the wafer backside. Laser scribing is performed on the wafer backside to cut through the mask, the die attach film and the wafer, including all layers included within the front side and backside of the wafer. A plasma etch is performed to treat or clean surfaces of the wafer exposed by the laser scribing. A wafer backside cleaning is performed and a second dicing tape is applied to the wafer backside. The protection tape is the removed from the wafer front side. | 06-26-2014 |
20140179108 | Wafer Edge Protection and Efficiency Using Inert Gas and Ring - Embodiments of the invention generally relate to an apparatus and method for plasma etching. In one embodiment, the apparatus includes a process ring with an annular step away from an inner wall of the ring and is disposed on a substrate support in a plasma process chamber. A gap is formed between the process ring and a substrate placed on the substrate support. The annular step has an inside surface having a height ranging from about 3 mm to about 6 mm. During operation, an edge-exclusion gas is introduced to flow through the gap and along the inside surface, so the plasma is blocked from entering the space near the edge of the substrate. | 06-26-2014 |
20140213041 | LASER AND PLASMA ETCH WAFER DICING WITH ETCH CHAMBER SHIELD RING FOR FILM FRAME WAFER APPLICATIONS - Laser and plasma etch wafer dicing where a mask is formed covering ICs formed on the wafer, as well as any bumps providing an interface to the ICs. The semiconductor wafer is coupled to a film frame by an adhesive film. The mask is patterned by laser scribing to provide a patterned mask with gaps. The laser scribing exposes regions of the semiconductor wafer, below thin film layers from which the ICs are formed. The semiconductor wafer is plasma etched through the gaps in the patterned mask while the film frame is maintained at an acceptably low temperature with a chamber shield ring configured to sit beyond the wafer edge and cover the frame. The shield ring may be raised and lowered, for example, on lifter pins to facilitate transfer of the wafer on frame. | 07-31-2014 |
20140256148 | METHOD AND APPARATUS FOR HIGH EFFICIENCY GAS DISSOCIATION IN INDUCTIVE COUPLED PLASMA REACTOR - Embodiments of the present disclosure relate to method and apparatus for providing processing gases to a process chamber with improved plasma dissociation efficiency. One embodiment of the present disclosure provides a baffle nozzle assembly comprising an outer body defining an extension volume connected to a processing chamber. A processing gas is flown to the processing chamber through the extension volume which is exposed to power source for plasma generation. | 09-11-2014 |
20140261805 | GAS DISTRIBUTION APPARATUS FOR DIRECTIONAL AND PROPORTIONAL DELIVERY OF PROCESS GAS TO A PROCESS CHAMBER - In some embodiments, a gas distribution apparatus may include: a manifold having a gas inlet to receive a process gas from a fast gas exchange unit and a first gas outlet to provide the process gas to a first gas delivery zone; a plurality of flow restrictors fluidly coupled to one another in parallel and to the gas inlet, wherein each of the plurality of flow restrictors are configured to allow at least a portion of a total flow of a process gas through each of the plurality of flow restrictors; and a plurality of valves each coupled to respective ones of the plurality of flow restrictors, wherein the plurality of valves are configured to be selectively opened to allow the process gas to flow through selective ones of the plurality of flow restrictors to provide a desired percentage of a total flow of the process gas to the outlet. | 09-18-2014 |
20140273401 | SUBSTRATE LASER DICING MASK INCLUDING LASER ENERGY ABSORBING WATER-SOLUBLE FILM - Methods of dicing substrates having a plurality of ICs. A method includes forming a mask comprising a laser energy absorbing material layer soluble in water over the semiconductor substrate. The laser energy absorbing material layer may be UV curable, and either remain uncured or be cured prior to removal with a water rinse. The mask is patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the substrate between the ICs. The substrate may then be plasma etched through the gaps in the patterned mask to singulate the IC with the laser energy absorbing mask protecting the ICs for during the plasma etch. The soluble mask is then dissolved subsequent to singulation. | 09-18-2014 |
20140273460 | PASSIVE CONTROL FOR THROUGH SILICON VIA TILT IN ICP CHAMBER - Embodiments of the present disclosure generally provide apparatus and methods for improving process result near the edge region of a substrate being processed. One embodiment of the present disclosure provides a cover ring for improving process uniformity. The cover ring includes a ring shaped body, and an extended lip extending radially inwards from the ring shaped body. An inner edge of the extended lip forms a central opening to expose a processing region on a substrate being processed, and a width of the extended lip is between about 15% to about 20% of a radius of the central opening. | 09-18-2014 |
20140363952 | LASER, PLASMA ETCH, AND BACKSIDE GRIND PROCESS FOR WAFER DICING - Front side laser scribing and plasma etch are performed followed by back side grind to singulate integrated circuit chips (ICs). A mask is formed covering ICs formed on the wafer, as well as any bumps providing an interface to the ICs. The mask is patterned by laser scribing to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer, below thin film layers from which the ICs are formed. The semiconductor wafer is then etched through the gaps in the patterned mask to advance a front of an etched trench partially through the semiconductor wafer thickness. The front side mask is removed, a backside grind tape applied to the front side, and a back side grind performed to reach the etched trench, thereby singulating the ICs. | 12-11-2014 |
20140367041 | WAFER DICING USING FEMTOSECOND-BASED LASER AND PLASMA ETCH - Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width. | 12-18-2014 |