Sanjay Havanur, Cupertino US
Sanjay Havanur, Cupertino, CA US
Patent application number | Description | Published |
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20090085656 | Device and Method for Limiting Di/Dt Caused by a Switching FET of an Inductive Switching Circuit - A circuit for limiting di/dt caused by a main switching FET during its turn-off against an inductive switching circuit is proposed. The circuit for limiting di/dt includes: | 04-02-2009 |
20090128223 | Thermally stable semiconductor power device - A semiconductor power device includes a circuit to provide a gate signal wherein the gate signal has a negative temperature coefficient of gate driving voltage for decreasing a gate driving voltage with an increase temperature whereby the semiconductor power device has a net Ids temperature coefficient that is less than or equal to zero. In an exemplary embodiment, the gate voltage driver includes a diode that has a negative forward voltage temperature coefficient connected between a gate and a source of the semiconductor power device. In another embodiment, the gate voltage is integrated with the semiconductor power device manufactured as part of an integrated circuit with the semiconductor power device. | 05-21-2009 |
20090130799 | Stacked dual MOSFET package - A method of fabricating a stacked dual MOSFET die package is disclosed. The method includes the steps of (a) forming a first conductive tab, (b) stacking a high side MOSFET die on the first conductive tab such that a drain contact of the high side MOSFET die is coupled to the first conductive tab, (c) stacking a second conductive tab in overlaying relationship to the high side MOSFET die such that a source contact of the high side MOSFET die is coupled to the second conductive tab, and (d) stacking a low side MOSFET die on the second conductive tab such that a drain contact of the low side MOSFET die is coupled to the second conductive tab. | 05-21-2009 |
20090243715 | Device and Method for Limiting Di/Dt Caused by a Switching FET of an Inductive Switching Circuit - A circuit for limiting di/dt caused by a main switching FET during its turn-off against an inductive switching circuit is proposed. The circuit for limiting di/dt includes: | 10-01-2009 |
20090279330 | Device and Method for Limiting Drain-Source Voltage of Transformer-Coupled Push Pull Power Conversion Circuit - A circuit is proposed for limiting maximum switching FET drain-source voltage (VDS) of a transformer-coupled push pull power converter with maximum DC supply voltage V | 11-12-2009 |
20100327947 | Circuit and Method for Controlling the Secondary FET of Transformer Coupled Synchronous Rectified Flyback Converter - A secondary FET | 12-30-2010 |
20110149620 | Device and Method for Limiting Drain-Source Voltage of Transformer-Coupled Push Pull Power Conversion Circuit - A circuit is proposed for limiting maximum switching FET drain-source voltage (VDS) of a transformer-coupled push pull power converter with maximum DC supply voltage V | 06-23-2011 |
20120205745 | Device and Associated Semiconductor Package for Limiting Drain-Source Voltage of Transformer-Coupled Push Pull Power Conversion Circuit - A circuit is proposed for limiting maximum switching FET drain-source voltage (VDS) of a transformer-coupled push pull power converter with maximum DC supply voltage V | 08-16-2012 |