Patent application number | Description | Published |
20090235209 | Manufacturability - Techniques are disclosed for modifying an existing microdevice design to improve its manufacturability. With these techniques, a designer receives manufacturing criteria associated with data in a design. The associated design data then is identified and provided to the microdevice designer, who may choose to modify the design based upon the manufacturing criteria. In this manner, the designer can directly incorporate manufacturing criteria from the foundry in the original design of the microdevice. | 09-17-2009 |
20140040850 | Manufacturability - Techniques are disclosed for modifying an existing microdevice design to improve its manufacturability. With these techniques, a designer receives manufacturing criteria associated with data in a design. The associated design data then is identified and provided to the microdevice designer, who may choose to modify the design based upon the manufacturing criteria. In this manner, the designer can directly incorporate manufacturing criteria from the foundry in the original design of the microdevice. | 02-06-2014 |
20140181765 | LOOK-UP BASED BUFFER TREE SYNTHESIS - Systems and techniques are described for performing buffer tree synthesis. Some embodiments create a lookup table based on information contained in a cell library. The lookup table is then used during buffer tree synthesis. | 06-26-2014 |
20140181777 | AUTOMATIC CLOCK TREE ROUTING RULE GENERATION - Systems and techniques are described for automatically generating a set of non-default routing rules for routing a net in a clock tree based on one or more metrics. The metrics can include a congestion metric, a latency metric, a crosstalk metric, an electromigration metric, and a clock tree level. Next, the embodiments can generate the set of non-default routing rules for routing the net based on one or more metrics. A routing rule can specify how wide the wires are supposed to be and how far apart adjacent wires are to be placed. A non-default routing rule can specify a wire width that is different from the default width and/or specify a spacing (i.e., the distance between two wires) that is different from the default spacing. | 06-26-2014 |
20140189627 | INCREMENTAL CLOCK TREE SYNTHESIS - Methods and apparatuses are described for optimizing local clock skew, and/or for synthesizing clock trees in an incremental fashion. For optimizing local clock skew, the circuit design can be partitioned into clock skew groups. Next, for each clock skew group, an initial clock tree can be constructed that substantially minimizes worst case clock skew in the clock skew group, and then the initial clock tree can be further optimized by substantially minimizing worst case local clock skew in the clock skew group. For performing incremental clock tree synthesis, a portion of a clock tree in the circuit design can be selected based on a set of modifications to the circuit design. Next, a new clock tree can be determined to replace the selected portion of the clock tree. The circuit design can then be modified by replacing the selected portion of the clock tree with the new clock tree. | 07-03-2014 |
20140237437 | LOOK-UP BASED FAST LOGIC SYNTHESIS - Systems and techniques are described for performing circuit synthesis. Some embodiments create a lookup table based on information contained in a cell library. The lookup table is then used during circuit synthesis. Specifically, some embodiments optimize cells in a reverse-levelized cell ordering. For a given cell, a table lookup is performed to obtain a set of optimal cell configurations, and the cell is replaced with a cell configuration selected from the set of optimal cell configurations. Some embodiments concurrently optimize cells for timing, area, and power leakage based on the timing criticality of the cells. | 08-21-2014 |
20140289690 | ON-CHIP-VARIATION (OCV) AND TIMING-CRITICALITY AWARE CLOCK TREE SYNTHESIS (CTS) - On-chip-variation (OCV) and timing-criticality aware clock tree synthesis (CTS) is described. Some embodiments can construct a first set of clock tree topologies for timing sequential circuit elements in a set of critical paths, wherein said constructing can comprise optimizing the first set of clock tree topologies to reduce an impact of OCV on clock skew. Next, the embodiments can construct a second set of clock tree topologies for timing sequential circuit elements that are not in the set of critical paths, wherein said constructing can comprise optimizing the second set of clock tree topologies to reduce latency, power consumption, and/or area. | 09-25-2014 |
20150089462 | CONCURRENT OPTIMIZATION OF TIMING, AREA, AND LEAKAGE POWER - Systems and techniques are described for performing circuit synthesis. Some embodiments create a lookup table based on information contained in a cell library. The lookup table is then used during circuit synthesis. Specifically, some embodiments optimize cells in a reverse-levelized cell ordering. For a given cell, a table lookup is performed to obtain a set of optimal cell configurations, and the cell is replaced with a cell configuration selected from the set of optimal cell configurations. Some embodiments concurrently optimize cells for timing, area, and power leakage based on the timing criticality of the cells. | 03-26-2015 |