Patent application number | Description | Published |
20090251961 | FLASH MEMORY DEVICE AND VOLTAGE GENERATING CIRCUIT FOR THE SAME - Disclosed is a flash memory device which includes a memory core, a high voltage generating circuit and a reference voltage generating circuit. The high voltage generating circuit is configured to generate a high voltage to be supplied to the memory core. The reference voltage generating circuit is configured to generate at least one reference voltage to be supplied to the high voltage generating circuit. The reference voltage generating circuit includes a first reference voltage generator configured to generate a first reference voltage in response to a supply voltage, and a second reference voltage generator configured to generate a second reference voltage in response to the first reference voltage. The at least one reference voltage supplied to the high voltage generating circuit includes the second reference voltage. | 10-08-2009 |
20120033501 | NONVOLATILE MEMORY DEVICE WITH 3D MEMORY CELL ARRAY - Disclosed is a nonvolatile memory device which includes a 3D memory cell array having words lines that extend from a lowest memory cell array layer closest to a substrate to a highest memory cell array layer farthest from the substrate, a voltage generator circuit generating first and second voltage signals, and a row selecting circuit that simultaneously applies the first voltage signal to a selected word line and the second voltage signal to an unselected word line. The selected word line and the unselected word line have different resistances, yet the first voltage signal is applied to the selected word line and the second voltage signal is applied to the unselected word line with a same rising slope over a defined period of time. | 02-09-2012 |
20120039120 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR PROGRAMMING THE DEVICE, AND MEMORY SYSTEM - A non-volatile memory device comprises a memory cell array comprising memory cells arranged in rows connected to corresponding word lines and columns connected to corresponding bit lines, a page buffer that stores a program data, a read-write circuit that programs and re-programs the program data into selected memory cells of the memory cell array and reads stored data from the programmed memory cells, and a control circuit that controls the page buffer and the read-write circuit to program the selected memory cells by loaded the program data from in page buffer and to re-program the selected memory cells by re-loaded the program data in the page buffer. | 02-16-2012 |
20120039130 | Nonvolatile Memory Devices, Channel Boosting Methods Thereof, Programming Methods Thereof, And Memory Systems Including The Same - Non-volatile memory device channel boosting methods in which at least two strings are connected to one bit line, the channel boosting methods including applying an initial channel voltage to channels of strings in a selected memory block, floating inhibit strings each having an un-programmed cell among the strings, and boosting channels of the floated inhibit strings. | 02-16-2012 |
20120047321 | Address Scheduling Methods For Non-Volatile Memory Devices With Three-Dimensional Memory Cell Arrays - At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where âkâ is 2 or a natural number greater than 2. | 02-23-2012 |
20120063235 | Memory Devices For Reducing Boosting Charge Leakage And Systems Including The Same - A three-dimensional (3D) non-volatile memory includes a memory cell array and a merge driver configured to apply a merge voltage at the same level to a common source line and a bulk in the memory cell array. | 03-15-2012 |
20120201080 | Nonvolatile Memory Devices And Driving Methods Thereof - Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions. | 08-09-2012 |
20120224426 | NONVOLATILE MEMORY DEVICE AND READ METHOD THEREOF - According to example embodiments, a read method of a nonvolatile memory device includes Disclosed is a read method of a nonvolatile memory device which includes selecting one of a plurality of vertical strings in a nonvolatile memory device, judging a channel length between a common source line and a selected one of the plurality of vertical strings, selecting a sensing manner corresponding to the judged channel length, and performing a sensing operation according to the selected sensing manner. The plurality of vertical strings may extend in a direction perpendicular to a substrate of the nonvolatile memory device. | 09-06-2012 |
20130007353 | CONTROL METHOD OF NONVOLATILE MEMORY DEVICE - According to example embodiments, a control method of a nonvolatile memory device, which includes a plurality of memory blocks on a substrate, each memory block including a plurality of sub blocks stacked in a direction perpendicular to the substrate and being configured to be erased independently and each sub block including a plurality of memory cells stacked in the direction perpendicular to the substrate. The control method includes comparing a count value of a first memory block with a reference value, the count value determined according to the number of program, read, or erase operations executed at the first memory block after data is programmed in the first memory block; and if the count value is greater than or equal to the reference value, performing a reprogram operation in which data programmed in first the memory block is read and the read data is programmed in a second memory block. | 01-03-2013 |
20130016561 | ERASE SYSTEM AND METHOD OF NONVOLATILE MEMORY DEVICEAANM NAM; Sang-WanAACI Hwaseong-siAACO KRAAGP NAM; Sang-Wan Hwaseong-si KR - An erase system and method of a nonvolatile memory device includes supplying an erase voltage to a plurality of memory cells of a nonvolatile memory, performing a read operation with a read voltage to word lines of the plurality of memory cells, and performing an erase verification operation with an erase verification voltage to at least one of the word lines of the plurality of memory cells, the erase verification voltage lower than the read voltage. | 01-17-2013 |
20130028027 | 3D SEMICONDUCTOR MEMORY DEVICE - A 3D semiconductor memory device including a plurality of memory cell strings, includes a substrate and a channel that extends from the substrate. Memory cells may be disposed in layers in which the diameter of the channel varies. A programming verification operation may be carried out in a sequence whereby memory cells more likely to fail in programming are verified before attempting to verify memory cells that are less likely to fail programming. In an exemplary embodiment, the verification operation is performed on a memory cell disposed in a layer associated with a larger-diameter channel before performing the verification on a memory cell disposed in a layer associated with a smaller-diameter channel. In an exemplary embodiment, if a verification process detects a programming failure, the verification of subsequent memory cells is cancelled. | 01-31-2013 |
20130083599 | NONVOLATILE MEMORY AND ERASING METHOD THEREOF - An erase method of a nonvolatile memory includes supplying an erase voltage to a substrate, supplying a selection word line voltage to word lines connected with a selected sub-block within a memory block of the nonvolatile memory, supplying a non-selection word line voltage to word lines connected with an unselected sub-block within the memory block during a first delay time from a point of time when the erase voltage is supplied, and thereafter floating the word lines connected with the unselected sub-block. | 04-04-2013 |
20130088921 | OPERATING METHOD OF NONVOLATILE MEMORY AND METHOD OF CONTROLLING NONVOLATILE MEMORY - An operating method of a nonvolatile memory, which includes a plurality of cell strings, each cell string having a plurality of memory cells and a string selection transistor stacked on a substrate, includes detecting threshold voltages of the string selection transistors of the plurality of cell strings; adjusting voltages to be supplied to the string selection transistors according to the detected threshold voltages; and applying the adjusted voltages to the string selection transistors to select or unselect the plurality of cell strings during a programming operation. | 04-11-2013 |
20130170297 | NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - According to example embodiments, a nonvolatile memory device includes a first and a second NAND string. The first NAND string includes a first string selection transistor, a first local ground and a first global ground selection transistor, and first memory cells stacked in a direction perpendicular to a substrate. The second NAND string includes a second string selection transistor, a second local ground and a second global ground selection transistor, and second memory cells stacked in the direction perpendicular to the substrate. The device includes a selection line driver including path transistors configured to select and provide at least one operation voltage to the first and second string selection transistors, the first and second local and global ground selection transistors. The first and second string selection transistors are electrically isolated from each other, and the first and second global ground selection transistors are electrically connected. | 07-04-2013 |
20130188423 | NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - According to example embodiments of inventive concepts, a nonvolatile memory device includes a first NAND string and a second NAND string. The first NAND string include a first string selection transistor, a first ground selection transistor having a threshold voltage higher than a threshold voltage of the first string selection transistor, and first memory cells stacked on a substrate. The a second NAND string includes a second string selection transistor, a second ground selection transistor having a threshold voltage higher than a threshold voltage of the second string selection transistor, and second memory cells stacked on the substrate. A first selection line may connect the first string selection line and the first ground selection line, and a second selection line may connect the second selection line and the second ground selection line. The first and second selection lines may be electrically isolated from each other. | 07-25-2013 |
20130235667 | NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A method is provided for programming a nonvolatile memory device, which includes multiple memory cells connected in series in a direction substantially perpendicular to a substrate. The method includes programming a first memory cell of the multiple memory cells, and programming a second memory cell of the multiple memory cells after the first memory cell is programmed, the second memory cell being closer to the substrate than the first memory cell. A diameter of a channel hole of the first memory cell is larger than a diameter of a channel hole of the second memory cell. | 09-12-2013 |
20130250677 | NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY SYSTEM, AND PROGRAM METHOD OF THE SAME - Disclosed is a method for programming a nonvolatile memory device, which includes memory cells arranged in a plurality of rows. The programming method includes alternately selecting word lines to program data at a first page portion and a second page portion associated with the memory cells. After the first and second page portions are programmed, the method includes programming data at a third page portion associated with the memory cells according to an order in which word lines are arranged. The word lines may be sequentially selected one by one from a word line adjacent to a ground selection line. | 09-26-2013 |
20130279260 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR PROGRAMMING THE DEVICE, AND MEMORY SYSTEM - A non-volatile memory device comprises a memory cell array comprising memory cells arranged in rows connected to corresponding word lines and columns connected to corresponding bit lines, a page buffer that stores a program data, a read-write circuit that programs and re-programs the program data into selected memory cells of the memory cell array and reads stored data from the programmed memory cells, and a control circuit that controls the page buffer and the read-write circuit to program the selected memory cells by loaded the program data from in page buffer and to re-program the selected memory cells by re-loaded the program data in the page buffer. | 10-24-2013 |
20130279262 | NONVOLATILE MEMORY DEVICES, CHANNEL BOOSTING METHODS THEREOF, PROGRAMMING METHODS THEREOF, AND MEMORY SYSTEMS INCLUDING THE SAME - Non-volatile memory device channel boosting methods in which at least two strings are connected to one bit line, the channel boosting methods including applying an initial channel voltage to channels of strings in a selected memory block, floating inhibit strings each having an un-programmed cell among the strings, and boosting channels of the floated inhibit strings. | 10-24-2013 |
20140233316 | MEMORY SYSTEM AND PROGRAMMING METHOD THEREOF - A program method of a nonvolatile memory device is provided, which includes programming a memory cell in one string selected from a plurality of vertical strings; determining whether a mode of operation of the nonvolatile memory device is a pre-pulse mode; when the mode of operation is determined to be the pre-pulse mode, applying a pre-pulse having a predetermined level to a string selection line connected with a gate of a string selection transistor of at least one unselected vertical string of the plurality of vertical strings for a particular time period; and performing a verification operation on the programmed memory cell. | 08-21-2014 |
20140293693 | MEMORY SYSTEM AND DRIVING METHOD THEREOF - A driving method of a nonvolatile memory device includes receiving a program command and an address. The method includes changing a number of adjacent zones of a plurality of zones formed of unselected word lines according to a location of a selected word line corresponding to the received address. The method further includes applying different zone voltages to the number of adjacent zones and remaining zones. The nonvolatile memory device includes a plurality of strings formed to penetrate word lines stacked on a substrate in a plate shape. | 10-02-2014 |
20140310448 | METHOD OF OPERATING MEMORY CONTROLLER AND DATA STORAGE DEVICE INCLUDING MEMORY CONTROLLER - In one embodiment, the method includes determining, at the memory controller, a status of a selected page of memory based on a program/erase cycle count for a block of the memory. The block of the memory includes the selected page. The program/erase cycle count indicates a number of times the block has been erased. The status is selected from a plurality of status states. The status states include a normal state, a weak state and a bad state. | 10-16-2014 |
20140334232 | 3D FLASH MEMORY DEVICE HAVING DIFFERENT DUMMY WORD LINES AND DATA STORAGE DEVICES INCLUDING SAME - A three-dimensional (3D) flash memory includes a first dummy word line disposed between a ground select line and a lowermost main word line, and a second dummy word line of different word line configuration disposed between a string select line and an upper most main word line. | 11-13-2014 |
20150009760 | THREE-DIMENSIONAL NONVOLATILE MEMORY AND RELATED READ METHOD DESIGNED TO REDUCE READ DISTURBANCE - A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground selection lines connected to the string selection transistors and the ground selection transistors, respectively. In the second interval, the device applies a turn-off voltage to unselected string selection lines and unselected ground selection lines while continuing to apply the turn-on voltage to a selected string selection line and a selected ground selection line. In both the first and second intervals, the device applies a first read voltage to a selected wordline connected to memory cells to be read by the read operation and applying a second read voltage to unselected wordlines among connected to memory cells not to be read by the read operation. | 01-08-2015 |
20150029790 | NONVOLATILE MEMORY AND ERASING METHOD THEREOF - An erase method of a nonvolatile memory includes supplying an erase voltage to a substrate, supplying a selection word line voltage to word lines connected with a selected sub-block within a memory block of the nonvolatile memory, supplying a non-selection word line voltage to word lines connected with an unselected sub-block within the memory block during a first delay time from a point of time when the erase voltage is supplied, and thereafter floating the word lines connected with the unselected sub-block. | 01-29-2015 |
20150078087 | CONTROL METHOD OF NONVOLATILE MEMORY DEVICE - According to example embodiments, a control method of a nonvolatile memory device, which includes a plurality of memory blocks on a substrate, each memory block including a plurality of sub blocks stacked in a direction perpendicular to the substrate and being configured to be erased independently and each sub block including a plurality of memory cells stacked in the direction perpendicular to the substrate. The control method includes comparing a count value of a first memory block with a reference value, the count value determined according to the number of program, read, or erase operations executed at the first memory block after data is programmed in the first memory block; and if the count value is greater than or equal to the reference value, performing a reprogram operation in which data programmed in first the memory block is read and the read data is programmed in a second memory block. | 03-19-2015 |
20150138890 | NONVOLATILE MEMORY DEVICES AND DRIVING METHODS THEREOF - Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions. | 05-21-2015 |
20150179235 | ERASE METHOD OF NONVOLATILE MEMORY DEVICE AND STORAGE DEVICE EMPLOYING THE SAME - A method of erasing a nonvolatile memory device which includes a plurality of memory blocks includes receiving an erase command; erasing a selected memory block among the plurality of memory blocks in response to the erase command; and performing an operation of checking whether a threshold voltage of a selection transistor connected to at least one selection line for selecting strings included in the selected memory block is changed while performing an erase verification operation for checking whether the selected memory block is normally erased. | 06-25-2015 |
20150179271 | NONVOLATILE MEMORY DEVICE AND METHOD OF ERASING NONVOLATILE MEMORY DEVICE - A method is provided for erasing a nonvolatile memory device, including multiple memory blocks formed in a direction perpendicular to a substrate, each memory block having multiple strings connected to a bit line. The method includes selecting a memory block to be erased using a power supply voltage; unselecting a remaining memory block, other than the selected memory block, using a negative voltage; setting a bias condition to reduce leakage currents of the unselected memory block; and performing an erase operation on the selected memory block. | 06-25-2015 |
20150187425 | NONVOLATILE MEMORY AND ERASING METHOD THEREOF - An erase method of a nonvolatile memory includes supplying an erase voltage to a substrate, supplying a selection word line voltage to word lines connected with a selected sub-block within a memory block of the nonvolatile memory, supplying a non-selection word line voltage to word lines connected with an unselected sub-block within the memory block during a first delay time from a point of time when the erase voltage is supplied, and thereafter floating the word lines connected with the unselected sub-block. | 07-02-2015 |
20150221373 | NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - According to example embodiments, an operation method of a nonvolatile memory device includes determining a location of a selected word line among word lines connected to the nonvolatile memory device, selecting one of a plurality of different read disturbance reducing modes according to the location of the selected word line, and performing a read or verification operation according to the selected read disturbance reducing modes. The nonvolatile memory device includes cell strings. Each one of the cell strings includes memory cells stacked on top of each other in a direction perpendicular to the substrate and between a ground select transistor and a string select transistor. The ground select transistor is between the substrate and the number of the memory cells. The string select transistor is connected to a bit line and is between the bit line and the number of the memory cells. | 08-06-2015 |
20150221375 | NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - In a method of programming a three-dimensional nonvolatile memory device, a program loop is executed at least one time, wherein the program loop includes a programming step for programming selected memory cells among the memory cells and a verifying step for verifying whether the selected memory cells are program-passed or not. In the programming the selected memory cells, a level of a voltage being applied to a common source line connected to the strings in common may be changed. Thus, in a program operation, power consumption which is needed to charge-discharge the common source line can be decreased while increasing boosting efficiency. | 08-06-2015 |
20150221376 | NONVOLATILE MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - A programming method is for programming a nonvolatile memory device including a plurality of strings disposed perpendicular to a substrate and connected between bitlines and a common source line. The programming method includes setting up the common source line to a predetermined voltage, floating the setup common source line, performing a program operation on memory cells connected to a selected wordline, and performing a verify operation on the memory cells. | 08-06-2015 |
20150221381 | MEMORY SYSTEM INCLUDING NONVOLATILE MEMORY DEVICE AN ERASE METHOD THEREOF - An erase method of a three-dimensional nonvolatile memory device may include receiving an erase command, applying an erase voltage to perform an erase operation to a selected memory region in response to the erase command, suspending the erase operation by cutting off the erase voltage after a specific time has elapsed from when the erase voltage is applied, receiving a resume command after a reference time has elapsed from when the erase operation is suspended, and applying the erase voltage to the memory region for the specific time according to the resume command. | 08-06-2015 |