Patent application number | Description | Published |
20080217681 | Charge trap memory device and method of manufacturing the same - Provided are a charge trap memory device and method of manufacturing the same. A charge trap memory device may include a tunnel insulating layer on a substrate, a charge trap layer on the tunnel insulating layer, and a blocking insulating layer formed of a material including Gd or a smaller lanthanide element on the charge trap layer. | 09-11-2008 |
20080296739 | Method of forming a thin film structure and stack structure comprising the thin film - Provided is a method of forming a thin film structure and a stack structure comprising the thin film. The method may include forming a crystalline Al | 12-04-2008 |
20090021979 | Gate stack, capacitorless dynamic random access memory including the gate stack and methods of manufacturing and operating the same - Provided are a gate stack, a capacitorless dynamic random access memory (DRAM) including the gate stack and methods of manufacturing and operating the same. The gate stack for a capacitorless DRAM may include a tunnel insulating layer on a substrate, a first charge trapping layer on the tunnel insulating layer, an interlayer insulating layer on the first charge trapping layer, a second charge trapping layer on the interlayer insulating layer, a blocking insulating layer on the second charge trapping layer, and a gate electrode on the blocking insulating layer. The capacitorless DRAM may include the gate stack on the substrate, and a source and a drain in the substrate on both sides of the gate stack. | 01-22-2009 |
20090034341 | Non-volatile memory devices and programming methods thereof including moving electrons through pad oxide layers between charge trap layers - Non-volatile memory devices and methods of programming a non-volatile memory device in which electrons are moved between charge trap layers through a pad oxide layer are provided. The non-volatile memory devices include a charge trap layer on a semiconductor substrate and storing electrons, a pad oxide layer on the first charge trap layer, and a second trap layer on the pad oxide layer and storing electrons. In a programming mode in which data is written, the stored electrons are moved between a first position of the first charge trap layer and a first position of the second charge trap layer through the pad oxide layer or between a second position of the first charge trap layer and a second position of the second charge trap layer through the pad oxide layer. | 02-05-2009 |
20090045455 | Nonvolatile memory device and method of fabricating the same - Example embodiments relate to nonvolatile semiconductor memory devices using an electric charge storing layer as a storage node and fabrication methods thereof. An electric charge trap type nonvolatile memory device may include a tunneling film, an electric charge storing layer, a blocking insulation film, and a gate electrode. The blocking insulation film may be an aluminum oxide having an energy band gap larger than that of a γ-phase aluminum oxide film. An α-phase crystalline aluminum oxide film as a blocking insulation film may have an energy band gap of about 7.0 eV or more along with fewer defects. The crystalline aluminum oxide film may be formed by providing a source film (e.g., AlF | 02-19-2009 |
20090050954 | Non-volatile memory device including charge trap layer and method of manufacturing the same - Provided are a non-volatile memory device and a method of manufacturing the non-volatile memory device. The non-volatile memory device includes a charge trap layer having a crystalline material. In the method, a tunneling insulating layer is formed on a substrate, and a crystalline charge trap layer is formed on the tunneling insulating layer. | 02-26-2009 |
20090061613 | Method of forming aluminum oxide layer and method of manufacturing charge trap memory device using the same - Provided is a method of forming an aluminum oxide layer and a method of manufacturing a charge trap memory device using the same. The method of forming an aluminum oxide layer may include forming an amorphous aluminum oxide layer on an underlying layer, forming a crystalline auxiliary layer on the amorphous aluminum oxide layer, and crystallizing the amorphous aluminum oxide layer. Forming the crystalline auxiliary layer may include forming an amorphous auxiliary layer on the amorphous aluminum oxide layer; and crystallizing the amorphous auxiliary layer. | 03-05-2009 |
20090067247 | Method of programming nonvolatile memory device - A method of programming a nonvolatile memory device may include applying a program voltage to a memory cell. A supplementary pulse may be applied to the memory cell to facilitate thermalization of charges after the application of the program voltage. A recovery voltage may be applied to the memory cell after the application of the supplementary pulse. A program state of the memory cell may be verified using a verification voltage after the application of the recovery voltage. | 03-12-2009 |
20090071934 | Crystalline aluminum oxide layers having increased energy band gap, charge trap layer devices including crystalline aluminum oxide layers, and methods of manufacturing the same - Crystalline aluminum oxide layers having increased energy band gap, charge trap memory devices including crystalline aluminum oxide layers and methods of manufacturing the same are provided. A method of forming an aluminum oxide layer having an increased energy band gap includes forming an amorphous aluminum oxide layer on a lower film, introducing hydrogen (H) or hydroxyl group (OH) into the amorphous aluminum oxide layer, and crystallizing the amorphous aluminum oxide layer including the H or OH. | 03-19-2009 |
20090078989 | Method of forming silicon nitride at low temperature, charge trap memory device including crystalline nano dots formed by using the same, and method of manufacturing the charge trap memory device - Provided are a method of forming silicon nitride at a low temperature, a charge trap memory device including crystalline nano dots formed by using the same, and a method of manufacturing the charge trap memory device. The method of forming silicon nitride includes loading a substrate into a chamber of a silicon nitride deposition device comprising a filament; increasing a temperature of the filament to a temperature whereby a reactant gas to be injected into the chamber may be dissociated; and injecting the reactant gas into the chamber so as to form a crystalline silicon nitride film or crystalline silicon nitride nano dots on the substrate. In the method, the temperature of the filament may be maintained at 1,400° C.˜2,000° C., and a pressure in the chamber may be maintained at several to several ten torr when the reactant gas in injected into the chamber. | 03-26-2009 |
20090115795 | INCREMENTAL BRIGHTNESS COMPENSATION SYSTEMS, DEVICES AND METHODS FOR ORGANIC LIGHT EMITTING DISPLAY (OLED) - An Organic Light Emitting Display (OLED) includes an array of OLED devices and an incremental OLED brightness compensation system/method. The incremental OLED brightness compensation system/method is configured to incrementally change an electrical supply of the array of OLED devices in response to monitoring a measure of variation between an actual brightness and a desired brightness of the array of OLED devices, so as to cause the OLED to incrementally attain the desired brightness. | 05-07-2009 |
20090184731 | Apparatus and method of adjusting driving voltage for selective pre-charge - An output of a driving circuit is controlled by selectively outputting a first voltage or a second voltage as an N-th output voltage level in response to a first control signal and an N-th input voltage level, where N is a natural number, and pre-charging the selected N-th output voltage level to a third voltage or a fourth voltage, in response to a second control signal, the pre-charging being preformed based on the selected N-th output voltage level and a newly input (N+1)th input voltage level. | 07-23-2009 |
20090230442 | Semiconductor apparatus and manufacturing method of the same - Provided is a semiconductor apparatus including a substrate region, an active region on the substrate region, a gate pattern on the active region, and first and second impurities-doped regions along both edges of the active region that do not overlap the gate pattern. The length of the first and second impurities-doped regions in the horizontal direction may be shorter than in the vertical direction. The first and second impurities-doped regions may be formed to be narrow along both edges of the active region so as not to overlap the gate pattern. | 09-17-2009 |
20090237140 | Voltage Adder Using Current Source - A voltage adder includes a first amplifier, a feedback resistor, and a control current source. The first amplifier includes a first input terminal to which a first voltage is input, a second input terminal connected to a feedback node, and an output terminal connected to an output node. The feedback resistor is connected between the output node and the feedback node. The control current source allows an addition current corresponding to a second voltage to flow through the feedback resistor. | 09-24-2009 |
20100097124 | Method of operating semiconductor device - Provided is a method of operating a semiconductor device, wherein an operating mode is set by adjusting timing of a voltage pulse or by adjusting a voltage level of the voltage pulse. | 04-22-2010 |
20100118623 | Method of operating semiconductor devices - A method of operating a semiconductor device including a memory cell of a 1-T DRAM is provided in which a gate voltage level in a hold mode is adjusted to adjust a data sensing margin of the semiconductor device. | 05-13-2010 |
20100118634 | Semiconductor apparatuses and methods of operating the same - A method of operating a semiconductor device is provided including applying a constant source voltage to a source line. | 05-13-2010 |
20100127759 | Method of operating semiconductor device - Provided is a method of operating a semiconductor device, in which a gate voltage or a drain voltage is adjusted in order to add carriers to or remove carriers from a body region, thereby realizing semiconductor having a plurality of data states. | 05-27-2010 |
20100133600 | Semiconductor devices having increased sensing margin - One transistor (1-T) dynamic random access memories (DRAM) having improved sensing margins that are relatively independent of the amount of carriers stored in a body region thereof. | 06-03-2010 |
20100133647 | Semiconductor devices and semiconductor device manufacturing methods - Semiconductor devices and semiconductor device manufacturing methods. The semiconductor device manufacturing methods may form a memory cell having a silicon on insulator (SOI) structure only in one or more localized regions of a bulk semiconductor substrate by use selective etching. Accordingly, a different bias voltage may be applied to a peripheral device than to a memory cell having the SOI structure. | 06-03-2010 |
20100135088 | Operation method of semiconductor device - Provided is a method of operating a semiconductor device, in which timing for switching each of a drain voltage pulse signal and a gate voltage pulse signal from a first state to a second state is controlled in an erase mode and a write mode. | 06-03-2010 |
20100177566 | Non-volatile memory device having stacked structure, and memory card and electronic system including the same - Provided are a non-volatile memory devices having a stacked structure, and a memory card and a system including the same. A non-volatile memory device may include a substrate. A stacked NAND cell array may have at least one NAND set and each NAND set may include a plurality of NAND strings vertically stacked on the substrate. At least one signal line may be arranged on the substrate so as to be commonly coupled with the at least one NAND set. | 07-15-2010 |
20120161277 | SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICE MANUFACTURING METHODS - Semiconductor devices and semiconductor device manufacturing methods. The semiconductor device manufacturing methods may form a memory cell having a silicon on insulator (SOI) structure only in one or more localized regions of a bulk semiconductor substrate by use selective etching. Accordingly, a different bias voltage may be applied to a peripheral device than to a memory cell having the SOI structure. | 06-28-2012 |
20130161727 | NON-VOLATILE MEMORY DEVICE HAVING STACKED STRUCTURE, AND MEMORY CARD AND ELECTRONIC SYSTEM INCLUDING THE SAME - Provided are a non-volatile memory devices having a stacked structure, and a memory card and a system including the same. A non-volatile memory device may include a substrate. A stacked NAND cell array may have at least one NAND set and each NAND set may include a plurality of NAND strings vertically stacked on the substrate. At least one signal line may be arranged on the substrate so as to be commonly coupled with the at least one NAND set. | 06-27-2013 |