Patent application number | Description | Published |
20110169542 | DELAY CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR DELAYING - A delay circuit of a semiconductor memory apparatus includes a decoding unit configured to decode a plurality of test signals and enable one of a plurality of control signals; a bias voltage generation unit configured to generate a first bias voltage and a second bias voltage depending upon the control signal enabled among the plurality of control signals; and a delay unit configured to determine a delay time depending upon levels of the first and second bias voltages, delay an input signal by the determined delay time, and output a resultant signal as an output signal. | 07-14-2011 |
20110187408 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus has a plurality of chips stacked therein, and generation timing of read control signals for controlling read operations of the plurality of stacked chips is controlled such that times after a read command is applied to when data are outputted from respective chips are made to substantially correspond to one another. | 08-04-2011 |
20110187429 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus has a plurality of chips stacked therein. Read control signals for controlling read operations of the plurality of chips are synchronized with a reference clock such that the time taken from the application of a read command to the output of data for each of the plurality of chips is maintained substantially the same. | 08-04-2011 |
20110204950 | DELAY CIRCUIT AND METHOD FOR DELAYING SIGNAL - A delay circuit includes: a delay unit configured to receive a clock signal, delay an input signal sequentially by a predetermined time interval, and output a plurality of first delayed signals; and an option unit configured to select one of the plurality of first delayed signals based on one or more select signals, and output a second delayed signal. | 08-25-2011 |
20110210780 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: a plurality of chips configured to receive an external voltage. Each one of the chips detects a signal delay characteristic of the one of the chips to generate an internal voltage having a level corresponding to the signal delay characteristic. | 09-01-2011 |
20110241763 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes an individual chip designating code setting block configured to generate a plurality of individual chip designating codes which have different code values or at least two of which have the same code value, in response to a plurality of chip fuse signals; and an individual chip activation block configured to compare the plurality of individual chip designating codes with chip selection address in response to the plurality of chip fuse signals, and enable one of a plurality of individual chip activation signals based on a result of the comparison. | 10-06-2011 |
20120057413 | SEMICONDUCTOR MEMORY APPARATUS AND TEST METHOD THEREOF - A semiconductor memory apparatus includes a clock control unit configured to receive a first clock when an enable signal is activated and generate a second clock which has a cycle closer in length to a target clock cycle than the first clock; a DLL input clock generation unit configured to output one of the first clock and the second clock as a DLL input clock according to a DLL select signal; and an address/command input clock generation unit configured to output one of the first clock and the second clock as an AC input clock according to the enable signal. | 03-08-2012 |
20120104388 | THREE-DIMENSIONAL STACKED SEMICONDUCTOR INTEGRATED CIRCUIT AND TSV REPAIR METHOD THEREOF - Provided is a | 05-03-2012 |
20120224441 | SEMICONDUCTOR MEMORY APPARATUS - Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, a semiconductor memory apparatus may include a page size control unit configured to generate first and second block enable signals having a level corresponding to one of a plurality of row selection signals or one of a plurality of column selection signals based on a page size control signal; a first page block configured to enable a plurality of first memory cells selected by the plurality of row selection signals in response to the first block enable signal, and activate data access of memory cells selected among the plurality of selected first memory cells by the plurality of column selection signals and the option column selection signal; and a second page block configured to enable a plurality of second memory cells selected by the plurality of row selection signals in response to the second block enable signal, and activate data access of memory cells selected among the plurality of selected second memory cells by the plurality of column selection signals and the option column selection signal. | 09-06-2012 |