| Patent application number | Description | Published |
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| 20100036634 | APPARATUS AND METHOD FOR GENERATING RESISTANCE CALIBRATION CODE IN SEMICONDUCTOR INTEGRATED CIRCUIT - A resistance calibration code generating apparatus includes a code calibration unit configured to calibrate and output code values of a resistance calibration code during predetermined cycles of a calibration clock, which are determined by a code calibration time control command, and a calibration clock generating unit configured to output the calibration clock using a code calibration command. | 02-11-2010 |
| 20100097877 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes an internal circuit configured to be driven by current flowing between first and second voltage nodes, and a current control unit configured to control an amount of the current in response to an operational-speed information signal. | 04-22-2010 |
| 20100308866 | SEMICONDUCTOR BUFFER CIRCUIT - A semiconductor buffer circuit that operates stably against PVT fluctuation is disclosed. The disclosed semiconductor buffer unit of the present invention includes: a detecting block configured to generate a plurality of code signals by detecting an external voltage, using a plurality of reference voltages; and a buffer unit configured to receive an input signal and the plurality of code signals and, based on the code signals, to generate an output signal, wherein a consumption of a driving current of the buffer unit is controlled based on the code signals. | 12-09-2010 |
| 20110102006 | CIRCUIT AND METHOD FOR TESTING SEMICONDUCTOR APPARATUS - A circuit for testing a semiconductor apparatus includes a test voltage applying unit configured to apply a test voltage to a first end of a through-silicon via (TSV) in response to a test mode signal and a detecting unit configured to be connected to a second end of the TSV and detect a current outputted from the second end of the TSV. | 05-05-2011 |
| 20110109382 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus having a plurality of semiconductor chips is configured in such a manner that the plurality of semiconductor chips share one or more source voltages generated in one of the plurality of semiconductor chips. | 05-12-2011 |
| 20110267137 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes an individual-chip-designating-code setting block configured to generate a plurality of sets of individual-chip-designating-codes which have different code values or in which at least two sets of individual-chip-designating-codes have the same code value, in response to a plurality of chip fuse signals; a control block configured to generate a plurality of enable control signals in response to the plurality of chip fuse signals and most significant bits of the plurality of sets of individual-chip-designating-codes; and an individual chip activation block configured to compare individual-chip-designating-codes of the plurality of sets of individual-chip-designating-codes excluding the most significant bits, with chip selection addresses in response to the plurality of enable control signals, and enable one of a plurality of individual-chip-activation-signals depending upon a comparison result. | 11-03-2011 |
| 20120119357 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus having stacked first and second chips includes a first through line of the first chip configured to receive a first coding signal and be electrically connected to a first through line of the second chip; a second through line of the first chip configured to receive a second coding signal; and a second through line of the second chip configured to be electrically connected to the first through line of the first chip and receive the first coding signal. | 05-17-2012 |
| 20120124408 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus may comprise: a first chip ID generation unit configured to receive an enable signal through a first through-silicon via and a clock signal through a second through-silicon via and generate a first chip ID signal and a delayed enable signal; a second chip ID generation unit configured to receive the delayed enable signal through a third through-silicon via from the first chip ID generation unit and the clock signal and generate a second chip ID signal; a first chip selection signal generation unit configured to receive the first chip ID signal and a main ID signal and generate a first chip selection signal; and a second chip selection signal generation unit configured to receive the second chip ID signal and the main ID signal and generate a second chip selection signal. | 05-17-2012 |
| 20120154008 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus may include a master chip, first to n | 06-21-2012 |
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| 20090067264 | SEMICONDUCTOR MEMORY DEVICE WITH NORMAL AND OVER-DRIVE OPERATIONS - A semiconductor memory device having a driver configured to sequentially perform over-driving and normal driving operations is presented. The semiconductor memory device includes a driver that outputs a drive signal, that over-drives the drive signal with an over-drive voltage having a voltage level higher than a normal drive voltage, and then subsequently normally drives the drive signal with the normal drive voltage. The semiconductor memory device also includes a drive voltage adjuster that detects a level of the over-drive voltage and compensates for a change in the voltage level of the normal drive voltage in response to the detected level of the over-drive voltage. | 03-12-2009 |
| 20100090721 | BUFFER OF SEMICONDUCTOR MEMORY APPARATUS - A buffer of a semiconductor memory apparatus includes a buffering section configured to generate an output signal by buffering an input signal. A mismatch compensation section generates a control voltage in correspondence with sizes of a second transistor of the same type as a first transistor constituting the buffering section, wherein the buffering section controls a transition time of the output signal in response to a level of the control voltage. | 04-15-2010 |
| 20100118619 | BUFFER CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A buffer circuit of a semiconductor memory apparatus includes a compensation voltage generation unit configured to generate a compensation voltage in response to a level of a reference voltage; and a buffering unit configured to generate an output signal by buffering an input signal depending on the reference voltage and control a transition section of the output signal depending on a level of the compensation voltage. | 05-13-2010 |
| 20100141332 | INTERNAL VOLTAGE GENERATOR OF SEMICONDUCTOR DEVICE - An internal voltage generator of a semiconductor device includes a charge pumping unit for performing a charge pumping operation on the basis of the voltage level of a reference voltage to generate a charge pumped voltage having a voltage level higher than the external power supply voltage; and an internal voltage generating unit for performing a charge pumping operation on the basis of an internal voltage level that is linear with respect to a temperature change in a first temperature range to generate an internal voltage, and to perform a charge pumping operation on the basis of an internal voltage clamping level that is constant independent of a temperature change in a second temperature range to generate the internal voltage. | 06-10-2010 |
| 20100237930 | INTERNAL VOLTAGE GENERATING APPARATUS AND METHOD FOR CONTROLLING THE SAME - The internal voltage generating apparatus includes a first charge pumping circuit, an external voltage level detector, and a second charge pumping circuit. The first charge pumping circuit outputs an internal voltage and selectively performs first charge pumping for the internal voltage depending on a result detecting a level of the internal voltage feed-backed. The external voltage level detector detects a level of an external voltage and outputs the result detecting the level of the internal voltage and outputs a result detecting the level of the external voltage as a detection signal. The second charge pumping circuit performs second charge pumping for the internal voltage together with the first charge pumping against a case in which the level of the external voltage is lower than a predetermined level by the detection signal of the external voltage level detector. | 09-23-2010 |
| 20100289556 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus that generates a voltage by performing a pumping operation in response to an oscillator signal includes a driving voltage detecting unit configured to control the cycle of the oscillator signal in accordance with the level of a driving voltage that is used to perform the pumping operation. | 11-18-2010 |
| 20110291229 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME - A semiconductor integrated circuit includes: a semiconductor chip; a through-chip via passing through a conductive pattern disposed in the semiconductor chip and cutting the conductive pattern; and an insulation pattern disposed on an outer circumference surface of the through-chip via to insulate the conductive pattern from the through-chip via. | 12-01-2011 |
| 20110291265 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING A MULTI-CHIP STRUCTURE - A semiconductor integrated circuit having a multi-chip structure includes a number of stacked semiconductor chips. Each of the semiconductor chips includes a first through electrode formed through the semiconductor chip, a first bump pad formed over the semiconductor chip at a region where the first bump pad is separated from the first through electrode, a first internal circuit formed inside the semiconductor chip, coupled to the first through electrode through a first metal path, and coupled to the first bump pad through a second metal path; and a redistribution layer (RDL) formed over a backside of the semiconductor chip. | 12-01-2011 |
| 20120007624 | SEMICONDUCTOR SYSTEM AND DEVICE FOR IDENTIFYING STACKED CHIPS AND METHOD THEREOF - A semiconductor system for identifying stacked chips includes a first semiconductor chip and a plurality of second semiconductor chips. The first semiconductor chip generates a plurality of counter codes by using an internal clock or an external input clock and transmits slave address signals and the counter codes through a through-chip via. The second semiconductor chips are given corresponding identifications (IDs) by latching the counter codes for a predetermined delay time, compare the latched counter codes with the slave address signals, and communicate data with the first semiconductor chip through the through-chip via according to the comparison result. | 01-12-2012 |
| 20120249229 | SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor integrated circuit includes a plurality of semiconductor chips respectively selected in response to a plurality of chip selection signals, and a chip selection signal generator configured to generate the chip selection signals in response to one first control signal for deciding whether to drive the semiconductor chips and at least one second control signal for selecting at least one semiconductor chip from among the semiconductor chips. | 10-04-2012 |
| 20120275251 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF - A semiconductor memory device includes a bit line sense amplification unit configured to sense/amplify data loaded on a bit line, and a driving control unit configured to supply a power line of the bit line sense amplification unit with an overdriving voltage in an overdriving period and supply an internal voltage line with a voltage of the power line of the bit line sense amplification unit in a discharge driving period. | 11-01-2012 |
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| 20110169542 | DELAY CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR DELAYING - A delay circuit of a semiconductor memory apparatus includes a decoding unit configured to decode a plurality of test signals and enable one of a plurality of control signals; a bias voltage generation unit configured to generate a first bias voltage and a second bias voltage depending upon the control signal enabled among the plurality of control signals; and a delay unit configured to determine a delay time depending upon levels of the first and second bias voltages, delay an input signal by the determined delay time, and output a resultant signal as an output signal. | 07-14-2011 |
| 20110187408 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus has a plurality of chips stacked therein, and generation timing of read control signals for controlling read operations of the plurality of stacked chips is controlled such that times after a read command is applied to when data are outputted from respective chips are made to substantially correspond to one another. | 08-04-2011 |
| 20110187429 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus has a plurality of chips stacked therein. Read control signals for controlling read operations of the plurality of chips are synchronized with a reference clock such that the time taken from the application of a read command to the output of data for each of the plurality of chips is maintained substantially the same. | 08-04-2011 |
| 20110204950 | DELAY CIRCUIT AND METHOD FOR DELAYING SIGNAL - A delay circuit includes: a delay unit configured to receive a clock signal, delay an input signal sequentially by a predetermined time interval, and output a plurality of first delayed signals; and an option unit configured to select one of the plurality of first delayed signals based on one or more select signals, and output a second delayed signal. | 08-25-2011 |
| 20110210780 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: a plurality of chips configured to receive an external voltage. Each one of the chips detects a signal delay characteristic of the one of the chips to generate an internal voltage having a level corresponding to the signal delay characteristic. | 09-01-2011 |
| 20110241763 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes an individual chip designating code setting block configured to generate a plurality of individual chip designating codes which have different code values or at least two of which have the same code value, in response to a plurality of chip fuse signals; and an individual chip activation block configured to compare the plurality of individual chip designating codes with chip selection address in response to the plurality of chip fuse signals, and enable one of a plurality of individual chip activation signals based on a result of the comparison. | 10-06-2011 |
| 20120057413 | SEMICONDUCTOR MEMORY APPARATUS AND TEST METHOD THEREOF - A semiconductor memory apparatus includes a clock control unit configured to receive a first clock when an enable signal is activated and generate a second clock which has a cycle closer in length to a target clock cycle than the first clock; a DLL input clock generation unit configured to output one of the first clock and the second clock as a DLL input clock according to a DLL select signal; and an address/command input clock generation unit configured to output one of the first clock and the second clock as an AC input clock according to the enable signal. | 03-08-2012 |
| 20120104388 | THREE-DIMENSIONAL STACKED SEMICONDUCTOR INTEGRATED CIRCUIT AND TSV REPAIR METHOD THEREOF - Provided is a | 05-03-2012 |
| 20120224441 | SEMICONDUCTOR MEMORY APPARATUS - Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, a semiconductor memory apparatus may include a page size control unit configured to generate first and second block enable signals having a level corresponding to one of a plurality of row selection signals or one of a plurality of column selection signals based on a page size control signal; a first page block configured to enable a plurality of first memory cells selected by the plurality of row selection signals in response to the first block enable signal, and activate data access of memory cells selected among the plurality of selected first memory cells by the plurality of column selection signals and the option column selection signal; and a second page block configured to enable a plurality of second memory cells selected by the plurality of row selection signals in response to the second block enable signal, and activate data access of memory cells selected among the plurality of selected second memory cells by the plurality of column selection signals and the option column selection signal. | 09-06-2012 |
