Patent application number | Description | Published |
20080285215 | MULTIMEDIA PORTABLE ELECTRONIC DEVICE - Disclosed is a multimedia portable electronic device including a first housing, a second housing coupled to the first housing so as to rotate about a first hinge axis, a third housing adapted to slide while facing the first housing, a fourth housing connected to the third housing so as to rotate about a second hinge axis to be folded/unfolded, a connection device positioned between the first and fourth housings so that the connection device rotates about a third hinge axis to slide the third housing when the fourth housing is folded on or unfolded from the third housing, and a sliding device positioned between the first and third housings so that the third housing can slide. | 11-20-2008 |
20120195150 | REFRESH CIRCUIT - A refresh circuit includes an enable pulse generator configured to generate a first enable pulse and a second enable pulse, a first address latch configured to latch the first row address in synchronization with the first enable pulse and generate a first latch address, and a second address latch configured to latch a second row address in synchronization with the second enable pulse and generate second and third latch addresses. | 08-02-2012 |
20120275247 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR REPAIRING THE SAME - A semiconductor memory device includes a latch address generation unit configured to latch row addresses to generate first and second latch addresses when at least one of memory cells coupled to sub word lines is faulty, wherein the first and second latch addresses select different main word lines, and a repair unit configured to perform a repair operation on memory cells coupled to the main word lines selected by the first and second latch addresses. | 11-01-2012 |
20130121097 | ADDRESS OUTPUT CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a signal generation unit configured to generate a toggling signal and first and second pulse signals in response to a test signal and a burst pulse signal. An address output unit may be configured to receive first to fourth input addresses and output sequentially first to fourth output addresses in response to the toggling signal and the first and second pulse signals. A repair unit may be configured to perform a repair operation on a word line selected by the first to fourth output addresses. | 05-16-2013 |
20130148458 | BUFFER CIRCUIT AND WORD LINE DRIVER USING THE SAME - A buffer circuit includes a pull-up element configured to pull-up drive a first node through which an output signal is outputted, in response to an input signal; a first voltage control element configured to reduce a voltage of the first node and set a voltage of a second node in a standby mode; and a pull-down element configured to pull-down drive the second node in response to the input signal. | 06-13-2013 |
20140177374 | DRIVER OF SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - A driver of a semiconductor memory device and driving method thereof is disclosed, which relates to a technology for reducing consumption of a leakage current not required for a driver circuit of a semiconductor memory device. The driver of the semiconductor memory device includes a drive controller configured to selectively provide a first voltage and a second voltage, that have different levels in response to a power-down signal, to a first node; an input driver configured to selectively output a voltage received from the first node in response to a decoding signal; and an output driver configured to be driven in response to an output voltage of the input driver. | 06-26-2014 |
20140369149 | WORD LINE DRIVERS AND SEMICONDUCTOR MEMORY DEVICES INCLUDING THE SAME - Word line drivers including a selection signal generator and a word line drive unit are provided. The selection signal generator generates a selection signal which is enabled according to a high-order address signal and a low-order address signal in an active mode. Further, the selection signal generator generates a complementary selection signal which is enabled when an equalization signal is inputted in a pre-charge mode after the active mode. The word line driver receives the main word line signal to drive a word line to have a first level when the selection signal is enabled, to drive the word line to have a second level when the selection signal is disabled, and to drive the word line to have a third level when the complementary selection signal is enabled. | 12-18-2014 |
20150036440 | SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME - Semiconductor devices are provided. The semiconductor device includes a counter configured to output a first internal address signal counted in synchronization with a refresh clock signal during a refresh operation, an address transmitter configured to output a first external signal as a second internal address signal in response to a refresh pulse, and a bank address generator configured to decode the first internal address signal or the second internal address signal in response to a selection signal to generate a bank address signal for accessing a bank. | 02-05-2015 |
20150046723 | SENSE-AMPLIFIER DRIVING DEVICE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A sense-amplifier driving device includes: a power-supply driving unit configured to respectively provide a first pull-up voltage and a first pull-down voltage to a pull-up power line and a pull-down power line during a first over-driving time section, and provide the first pull-up voltage to the pull-up power line during a second over-driving time section; an over-driving controller configured to provide a second pull-down voltage lower than the first pull-down voltage to the pull-down power line during the second over-driving time section; and a drive-signal generator configured to generate a drive signal activated for the first and second over-driving time sections so as to control driving of the power-supply driving unit. | 02-12-2015 |
20150071014 | DATA TRAINING DEVICE - A data training device includes a training control block configured to activate driving signals for driving a bit line sense amplifier, with a word line deactivated, when a write training operation is performed according to a mode register write command; and the bit line sense amplifier configured to store training data according to the driving signals from the training control block. | 03-12-2015 |