Patent application number | Description | Published |
20100091602 | ADDRESS COUNTING CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME - An address counting circuit includes a counter configured to sequentially count from an initial address in response to a clock signal in order to output counted addresses. The address counting circuit also includes a code conversion unit that is configured to output converted addresses such that only one address bit of the converted addresses with respect to the previous converted addresses are toggled to output the converted addresses. The converted addresses output form the code conversion unit do not overlap with one another. | 04-15-2010 |
20110001552 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first transmission line and a second transmission line disposed at different layers; a contact fuse coupled with the first transmission line and the second transmission line; a power driver configured to apply an electric stress to the contact fuse; and a fuse state output unit configured to output a fuse state signal having a logic level corresponding to an electric connection state of the contact fuse. | 01-06-2011 |
20110001559 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor device and a method for driving the same rapidly detect failure of a through-semiconductor-chip via and effectively repairing the failure using a latching unit assigned to each through-semiconductor-chip via. The semiconductor device includes a plurality of semiconductor chips that are stacked, and a plurality of through-semiconductor-chip vias to commonly transfer a signal to the plurality of semiconductor chips, wherein each of the semiconductor chips includes a multiplicity of latching units assigned to the through-semiconductor-chip vias and the multiplicity of latching units of each of the semiconductor chips constructs a boundary scan path including the plurality of through-semiconductor-chip vias to sequentially transfer test data. | 01-06-2011 |
20110006391 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of stacked semiconductor chips; and a plurality of through-silicon vias (TSVs) including first TSVs and redundant TSVs and configured to commonly transfer a signal to the plurality of stacked semiconductor chips. At least one of the semiconductor chips includes a plurality of repair fuse units configured to store defect information as to at least one defect of the TSVs; and a plurality of latch units allocated to the respective TSVs and configured to store a plurality of signals indicating at least one TSV defect and outputted from the plurality of repair fuse units. | 01-13-2011 |
20110161581 | SEMICONDUCTOR CIRCUIT APPARATUS - A semiconductor circuit apparatus having a commonly shared control unit that coordinates reading and writing timed activities in two ranked subcircuits is presented. The semiconductor circuit includes: first and second ranks; and a rank control block shared by the first and second ranks and configured to provide a column-related command and an address to one of the first and second ranks in response to a chip select signal for selecting the first or second rank. | 06-30-2011 |
20120092062 | SEMICONDUCTOR SYSTEM - A semiconductor system includes a controller; a semiconductor device comprising a plurality of stacked semiconductor chips stacked over the controller, and a plurality of through-silicon vias (TSVs) configured to commonly transfer a signal to the plurality of stacked semiconductor chips; and a defect information transfer TSV configured to transfer TSV defect information sequentially outputted from at least one of the semiconductor chips to the controller, wherein the controller comprises: a plurality of first repair fuse units configured to set first fuse information based on the TSV defect information; and a plurality of first TSV selection units configured to selectively drive the TSVs in response to the first fuse information. | 04-19-2012 |
20120155200 | MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND CONTROL METHOD THEREOF - A memory system includes a memory device, a control device configured to control the memory device, a first channel configured to transfer a row command from the control device to the memory device, and a second channel configured to transfer a column command from the control device to the memory device. | 06-21-2012 |
20120217654 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a wafer comprising a chip that passes a test and a chip that does not pass a test, one or more first stacked chips that are stacked over the chip that passes a test, and one or more second stacked chips that are stacked over the chip that does not pass a test, wherein the second stacked chips comprise at least one between an chip that does not pass a test and a dummy chip. | 08-30-2012 |
20120266034 | SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREOF - A semiconductor memory device includes a plurality of memory cells; a data comparison section configured to compare input data to be stored in the memory cells with output data outputted from the memory cells in a test operation, an address storage section configured to store addresses corresponding to defected memory cells of the memory cells in response to a comparison result of the data comparison section, and a comparison period control section configured to generate a period control signal for controlling an activation period of the data comparison section. | 10-18-2012 |
20120269018 | MEMORY SYSTEM HAVING MEMORY AND MEMORY CONTROLLER AND OPERATION METHOD THEREOF - An operation method of a memory system including a memory and a memory controller includes transmitting defective-cell address information to the memory controller from the memory at an initial operation of the memory, wherein the defective-cell address information includes an address of a defective cell of the memory, and accessing, by the memory controller, an area of the memory excluding an area indicated by the defective-cell address information inside the memory. | 10-25-2012 |
20130214389 | INTEGRATED CIRCUIT - An integrated circuit includes a first chip having a plurality of through-chip vias, and a second chip stacked on the first chip and having a plurality of through-chip vias which are disposed at positions corresponding to the plurality of through-chip vias of the first chip and each of which is connected with at least one through-chip via of the first chip arranged in an oblique direction, which is not on a straight line extending in a chip stacking direction, among the plurality of through-chip vias of the first chip, wherein the first chip inputs/outputs a signal through a through-chip via which is selected by first repair information among the plurality of through-chip vias of the first chip, and the second chip inputs/outputs a signal through a through-chip via which is selected by second repair information among the plurality of through-chip vias of the second chip. | 08-22-2013 |
20140291855 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor device includes a plurality of semiconductor chips in a stack structure and a through-silicon via suitable for passing through the chips and transfer a signal from or to one or more of the chips. Each of the chips includes a buffering block disposed in path of the through-silicon via, and suitable for buffering the signal, an internal circuit, and a delay compensation block suitable for applying delay corresponding to the buffering blocks of the chips to the signal, wherein the delay compensation blocks of the chips compensates for delay difference of the signal transferred to and from the internal circuit of the chip, due to operations of the buffering block, based on stack information for distinguishing the chips. | 10-02-2014 |
20150060854 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a main region suitable for performing a first test operation and a second test operation respectively based on a first test signal and a second test signal in a test mode, a first test region electrically connected to the main region and suitable for generating and transferring the first test signal to the main region in the test mode, and a second test region electrically connected to the main region or the first test region with a scribe lane disposed therebetween and suitable for generating and transferring the second test signal to the main region in the test mode. | 03-05-2015 |