| Patent application number | Description | Published |
|---|
| 20080285359 | Level-shifter circuit and memory device comprising said circuit - A level-shifter circuit is adapted for shift an input voltage into an output voltage that is variable between a negative voltage value up to a preset positive voltage level. The shifter circuit includes a first circuit adapted to shift the input voltage into the preset positive voltage level, a second circuit adapted to transfer the preset voltage level to a third circuit connected to a preset negative voltage value. The third circuit is connected to a further voltage at a positive or nil level and is adapted to supply an output voltage to the preset negative level or to the positive or nil level. | 11-20-2008 |
| 20090154249 | SENSE AMPLIFIER FOR LOW-SUPPLY-VOLTAGE NONVOLATILE MEMORY CELLS - A sense amplifier for nonvolatile memory cells includes a reference cell, a first load, connected to the reference cell, and a second load, connectable to a nonvolatile memory cell, both the first load and the second load having controllable resistance; a control circuit of the first load and of the second load supplies the first load and the second load with a control voltage irrespective of an operating voltage between a first conduction terminal and a second conduction terminal of the first load. | 06-18-2009 |
| 20100020594 | DEVICE FOR PROGRAMMING A PCM CELL WITH DISCHARGE OF CAPACITANCE AND METHOD FOR PROGRAMMING A PCM CELL - A device for programming PCM cells includes a pulse-generator circuit for supplying programming current pulses. The pulse-generator circuit includes: at least one first capacitive element; a charging circuit, connectable to the first capacitive element in a first operating condition, for bringing a reference voltage on the first capacitive element to a reset value; a discharge-current generator, selectively connectable to the first capacitive element in a second operating condition, for discharging the first capacitive element through a controlled discharge current; a logic unit, configured to control connection and disconnection of the first capacitive element), of the charging circuit, and of the discharge-current generator; and a voltage-to-current converter, for converting the reference voltage into current. | 01-28-2010 |
| 20100054031 | COLUMN DECODER FOR NON-VOLATILE MEMORY DEVICES, IN PARTICULAR OF THE PHASE-CHANGE TYPE - A column decoder is for a phase-change memory device provided with an array of memory cells, a reading stage for reading data contained in the memory cells, and a programming stage for programming the data. The column decoder selects and enables biasing of a bitline of the array and generates a current path between the bitline and the reading stage or, alternatively, the programming stage, respectively during a reading or a programming operation of the contents of the memory cells. In the column decoder, a first decoder circuit generates a first current path between the bitline and the reading stage, and a second decoder circuit, distinct and separate from the first decoder circuit, generates a second current path, distinct from the first current path, between the bitline and the programming stage. | 03-04-2010 |
| 20100054032 | ROW DECODER FOR NON-VOLATILE MEMORY DEVICES, IN PARTICULAR OF THE PHASE-CHANGE TYPE - A hierarchical row decoder is for a phase-change memory device provided with an array of memory cells organized according to a plurality of array wordlines and array bitlines. The row decoder has a global decoder that addresses first and a second global wordlines according to first address signals; and a local decoder, which is operatively coupled to the global decoder and addresses a respective array wordline according to the value the first and second global wordline and second address signals. The local decoder has a first circuit branch providing, when the first global wordline is addressed, a first current path between the array wordline and a first biasing source during a reading operation; and a second circuit branch providing, when the second global wordline is addressed, a second current path, distinct from the first current path, between the array wordline and a second biasing source during a programming operation. | 03-04-2010 |
| 20100163833 | ELECTRICAL FUSE DEVICE BASED ON A PHASE-CHANGE MEMORY ELEMENT AND CORRESPONDING PROGRAMMING METHOD - A fuse device has a fuse element provided with a first terminal and a second terminal and an electrically breakable region, which is arranged between the first terminal and the second terminal and is configured to undergo breaking as a result of the supply of a programming electrical quantity, thus electrically separating the first terminal from the second terminal. The electrically breakable region is of a phase-change material, in particular a chalcogenic material, for example GST. | 07-01-2010 |
| 20110156785 | TRIMMING OF A PSEUDO-CLOSED LOOP PROGRAMMABLE DELAY LINE - An embodiment is proposed for trimming a programmable delay line in an integrated device, which delay line is adapted to delay an input signal being synchronous with a synchronization signal of the integrated device—by a total delay. An embodiment of a corresponding method includes the steps of: preliminary programming the delay line to provide a selected nominal value of the total delay equal to a period of the timing signal, and trimming the delay line to vary an actual value of the total delay until the actual value of the total delay matches the period of the synchronization signal. | 06-30-2011 |
