Patent application number | Description | Published |
20100244106 | Fabrication and structure of asymmetric field-effect transistors using L-shaped spacers - Fabrication of an asymmetric field-effect transistor ( | 09-30-2010 |
20100244128 | Configuration and fabrication of semiconductor structure using empty and filled wells - A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors (“IGFETs”), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs ( | 09-30-2010 |
20100244130 | Structure and fabrication of field-effect transistor using empty well in combination with source/drain extensions or/and halo pocket - Insulated-gate field-effect transistors (“IGFETs”), both symmetric and asymmetric, suitable for a semiconductor fabrication platform that provides IGFETs for analog and digital applications, including mixed-signal applications, utilize empty-well regions in achieving high performance. A relatively small amount of semiconductor well dopant is near the top of each empty well. Each IGFET ( | 09-30-2010 |
20100244131 | Structure and fabrication of asymmetric field-effect transistor having asymmetric channel zone and differently configured source/drain extensions - An asymmetric insulated-gate field-effect transistor ( | 09-30-2010 |
20100244147 | Configuration and fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portions along source/drain zone - An asymmetric insulated-gate field effect transistor ( | 09-30-2010 |
20100244149 | Structure and fabrication of like-polarity field-effect transistors having different configurations of source/drain extensions, halo pockets, and gate dielectric thicknesses - A group of high-performance like-polarity insulated-gate field-effect transistors ( | 09-30-2010 |
20100244150 | Configuration and fabrication of semiconductor structure in which source and drain extensions of field-effect transistor are defined with different dopants - An insulated-gate field-effect transistor ( | 09-30-2010 |
20100244152 | Configuration and fabrication of semiconductor structure having extended-drain field-effect transistor - An extended-drain insulated-gate field-effect transistor (104 or 106) contains first and second source/drain zones 324 and 184B or 364 and 186B) laterally separated by a channel (322 or 362) zone constituted by part of a first well region (184A or 186A). A gate dielectric layer (344 or 384) overlies the channel zone. A gate electrode (346 or 386) overlies the gate dielectric layer above the channel zone. The first source/drain zone is normally the source. The second S/D zone, normally the drain, is constituted with a second well region (184B or 186B). A well-separating portion 186A or 186B/212U) of the semiconductor body extends between the well regions and is more lightly doped than each well region. The configuration of the well regions cause the maximum electric field in the IGFET's portion of the semiconductor body to occur well below the upper semiconductor surface, typically at or close to where the well regions are closest to each other. The IGFET's operating characteristics are stable with operational time. | 09-30-2010 |
20110108926 | Gated anti-fuse in CMOS process - In a gated anti-fuse, an anode is separated from a cathode by an oxide layer and the anode or cathode voltage is controlled by the control gate of a transistor like structure connected to the anode or cathode. | 05-12-2011 |
20110284859 | Growth of group III nitride- based structures and integration with conventional CMOS processing tools - A method includes forming a non-continuous epitaxial layer over a semiconductor substrate. The substrate includes multiple mesas separated by trenches. The epitaxial layer includes crystalline Group III nitride portions over at least the mesas of the substrate. The method also includes depositing a dielectric material in the trenches. The method could also include forming spacers on sidewalls of the mesas and trenches or forming a mask over the substrate that is open at tops of the mesas. The epitaxial layer could also include Group III nitride portions at bottoms of the trenches. The method could further include forming gate structures, source and drain contacts, conductive interconnects, and conductive plugs over at least one crystalline Group III nitride portion, where at least some interconnects and plugs are at least partially over the trenches. The gate structures, source and drain contacts, interconnects, and plugs could be formed using standard silicon processing tools. | 11-24-2011 |
20120056244 | Growth of multi-layer group III-nitride buffers on large-area silicon Substrates and other substrates - A method includes forming a first epitaxial layer over a semiconductor substrate and etching the first epitaxial layer to form multiple separated first epitaxial regions. The method also includes forming a second epitaxial layer over the etched first epitaxial layer. Each epitaxial layer includes at least one Group III-nitride, and the epitaxial layers collectively form a buffer. The method further includes forming a device layer over the buffer and fabricating a semiconductor device using the device layer. The second epitaxial layer could include second epitaxial regions substantially only on the first epitaxial regions. The second epitaxial layer could also cover the first epitaxial regions and the substrate, and the second epitaxial layer may or may not be etched. The device layer could be formed during the same operation used to form the second epitaxial layer. | 03-08-2012 |
20120184077 | Configuration and Fabrication of Semiconductor Structure in Which Source and Drain Extensions of Field-effect Transistor Are Defined with Different Dopants - An insulated-gate field-effect transistor ( | 07-19-2012 |
20120223317 | OHMIC CONTACT SCHEMES FOR GROUP III-V DEVICES HAVING A TWO-DIMENSIONAL ELECTRON GAS LAYER - A semiconductor device includes a first layer and a second layer over the first layer. The first and second layers are configured to form an electron gas layer at an interface of the first and second layers. The semiconductor device also includes an Ohmic contact and multiple conductive vias through the second layer. The conductive vias are configured to electrically couple the Ohmic contact to the electron gas layer. The conductive vias could have substantially vertical sidewalls or substantially sloped sidewalls, or the conductive vias could form a nano-textured surface on the Ohmic contact. The first layer could include Group III-nitride nucleation, buffer, and channel layers, and the second layer could include a Group III-nitride barrier layer. | 09-06-2012 |
20120264263 | Structure and Fabrication of Like-polarity Field-effect Transistors Having Different Configurations of Source/Drain Extensions, Halo Pockets, and Gate Dielectric Thicknesses - A group of high-performance like-polarity insulated-gate field-effect transistors ( | 10-18-2012 |
20120280281 | GALLIUM NITRIDE OR OTHER GROUP III/V-BASED SCHOTTKY DIODES WITH IMPROVED OPERATING CHARACTERISTICS - A semiconductor device includes a first Group III/V layer and a second Group III/V layer over the first Group III/V layer. The first and second Group III/V layers are configured to form an electron gas layer. The semiconductor device also includes a Schottky electrical contact having first and second portions. The first portion is in sidewall contact with the electron gas layer. The second portion is over the second Group III/V layer and is in electrical connection with the first portion of the Schottky electrical contact. The first portion of the Schottky electrical contact and the first or second Group III/V layer can form a Schottky barrier, and the second portion of the Schottky electrical contact can reduce an electron concentration near the Schottky barrier under reverse bias. | 11-08-2012 |
20130015535 | Configuration and Fabrication of Semiconductor Structure Having Asymmetric Field-effect Transistor with Tailored Pocket Portion Along Source/Drain Zone - An asymmetric insulated-gate field effect transistor ( | 01-17-2013 |
20140042458 | GROWTH OF MULTI-LAYER GROUP III-NITRIDE BUFFERS ON LARGE-AREA SILICON SUBSTRATES AND OTHER SUBSTRATES - A method includes forming a first epitaxial layer over a semiconductor substrate and etching the first epitaxial layer to form multiple separated first epitaxial regions. The method also includes forming a second epitaxial layer over the etched first epitaxial layer. Each epitaxial layer includes at least one Group III-nitride, and the epitaxial layers collectively form a buffer. The method further includes forming a device layer over the buffer and fabricating a semiconductor device using the device layer. The second epitaxial layer could include second epitaxial regions substantially only on the first epitaxial regions. The second epitaxial layer could also cover the first epitaxial regions and the substrate, and the second epitaxial layer may or may not be etched. The device layer could be formed during the same operation used to form the second epitaxial layer. | 02-13-2014 |
20140051226 | GROWTH OF MULTI-LAYER GROUP III-NITRIDE BUFFERS ON LARGE-AREA SILICON SUBSTRATES AND OTHER SUBSTRATES - A method includes forming a first epitaxial layer over a semiconductor substrate and etching the first epitaxial layer to form multiple separated first epitaxial regions. The method also includes forming a second epitaxial layer over the etched first epitaxial layer. Each epitaxial layer includes at least one Group III-nitride, and the epitaxial layers collectively form a buffer. The method further includes forming a device layer over the buffer and fabricating a semiconductor device using the device layer. The second epitaxial layer could include second epitaxial regions substantially only on the first epitaxial regions. The second epitaxial layer could also cover the first epitaxial regions and the substrate, and the second epitaxial layer may or may not be etched. The device layer could be formed during the same operation used to form the second epitaxial layer. | 02-20-2014 |
20140374766 | BI-DIRECTIONAL GALLIUM NITRIDE SWITCH WITH SELF-MANAGED SUBSTRATE BIAS - A semiconductor device includes a bidirectional GaN FET formed on a non-insulating substrate. The semiconductor device further includes a first electrical clamp connected between the substrate and a first source/drain node of the bidirectional GaN FET, and a second electrical clamp connected between the substrate and a second source/drain node of the bidirectional GaN FET. The first clamp and the second clamp are configured to bias the substrate at a lower voltage level of an applied bias to the first source/drain node and an applied bias to the second source/drain node, within an offset voltage of the relevant clamp. | 12-25-2014 |