Patent application number | Description | Published |
20100031215 | System and Method for Improved Placement in Custom VLSI Circuit Design with Schematic-Driven Placement - A method for generating an electronic circuit layout with placed circuit elements receives a user provided schematic, the user provided schematic comprising a plurality of circuit elements, each circuit element comprising general parameters. The method associates a plurality of first placement parameters with each of the plurality of circuit elements, wherein the first placement parameters comprise a cell horizontal position, a cell vertical stacking position, and a cell vertical adjacent spacing. The method retrieves, from a design library, design parameters associated with at least one of the plurality of circuit elements. The method assigns first absolute placement coordinates for each of the plurality of circuit elements based on the first placement parameters and the design parameters. The method defines and performs an adjustment operation on the placement parameters of a selected subset of circuit elements, generating adjusted placement parameters. The method assigns second absolute placement coordinates based on the first placement parameters, the design parameters, and the adjusted placement parameters and generates an electronic circuit layout with placed circuit elements based on the second absolute placement coordinates. | 02-04-2010 |
20100031218 | System and Method for Automated Placement in Custom VLSI Circuit Design with Schematic-Driven Placement - A method for automatically generating an electronic circuit layout with placed circuit elements includes receiving a user provided schematic, the user provided schematic comprising a plurality of circuit elements, each circuit element comprising general parameters. The method associates a plurality of first placement parameters with each of the plurality of circuit elements. The method retrieves, from a design library, design parameters associated with at least one of the plurality of circuit elements. The method selects a subset of circuit elements and receives placement inputs. The method generates a first placed layout configuration comprising adjusted placement parameters, based on the received placement inputs, the first placement parameters, and the design parameters. The method assigns absolute placement coordinates for each of the plurality of circuit elements based on the first placed layout configuration. The method generates an electronic circuit layout with placed circuit elements based on the absolute placement coordinates. | 02-04-2010 |
20100185552 | PROVIDING GPS-BASED LOCATION AND TIME INFORMATION - Methods and apparatus, including computer program products, implementing and using techniques for providing data pertaining to a one or more users' visits to an establishment. A location of one or more global positioning system devices is determined. Each global positioning system device is associated with a user of the device. One or more establishments situated at each determined location are identified. One or more of a time of day and a duration of the user's visit to the establishment is determined. One or more of the location, the time of day and the duration of the user's visit are recorded in a database. | 07-22-2010 |
20110072090 | METHOD AND SYSTEM FOR NAVIGATING EMAIL - A method and computer program product for providing an email navigation tool includes receiving, on an email server, an email thread including a sequence of email messages. A sender of each email message in the sequence of email messages is identified. At least one sender file associated with at least one identified sender of the email messages in the sequence of email messages is identified. The sender file is configured to provide a visual identification of the identified sender. A sequence of sender files is generated from the at least one sender file. The sequence of sender files has an order corresponding to an order of the sequence of email messages. The sequence of sender files is displayed on a computer display. | 03-24-2011 |
20110119581 | RECORDING EVENTS IN A VIRTUAL WORLD - Systems, methods and articles of manufacture are disclosed for recording events occurring in a virtual world. In one embodiment, properties of events previously recorded and/or attended by a user may be identified. Recording criteria for the user may be derived from the identified properties. Upon identifying an event satisfying the recording criteria, the event may be recorded. The recorded event may be played back at the convenience of the user. | 05-19-2011 |
20110141826 | Cache Array Power Savings Through a Design Structure for Valid Bit Detection - A mechanism is provided for gating a read access of any row in a cache access memory that has been invalidated. An address decoder in the cache access memory sends a memory access to a non-gated wordline driver and a gated wordline driver associated with the memory access. The non-gated wordline driver outputs the data stored in a valid bit memory cell to the gated wordline driver in response to the non-gated wordline driver determining the memory access as a read access. The gated wordline driver determines whether the data from the valid bit memory cell from the non-gated wordline driver indicates either valid data or invalid data in response to the gated wordline driver determining the memory access as a read access and denies an output of the data in a row of memory cells associated with the gated wordline driver in response to the data being invalid. | 06-16-2011 |
20120046921 | CIRCUIT DESIGN OPTIMIZATION - A method includes generating a first behavioral model of a circuit, the first behavioral model describing a physical circuit in a first configuration. The first configuration comprises a first logic structure configured to generate a first intermediate signal based on a received first plurality of inputs. The first configuration further comprises a logic cone configured to generate a scan output based on the first intermediate signal and a plurality of scan inputs. The first behavioral model is modified to generate a second behavioral model describing the physical circuit in a second configuration. The second configuration comprises an error circuit configured to receive the scan output and the first intermediate signal. A testability model is generated based on the second behavioral model, the testability model comprising a first structural representation of the first logic structure. In the event the first logic structure causes a coverage problem, the testability model is modified to include an inversion structure. The inversion structure is configured based on the first logic structure. The inversion structure is configured to generate an inversion structure output. The testability model is modified to couple the inversion structure output as an input to the error circuit. | 02-23-2012 |
20120047476 | CIRCUIT DESIGN OPTIMIZATION - A method comprises generating a first behavioral model of a circuit describing a physical circuit in a first configuration. The first configuration comprises a first master latch, a first fanout path, and a logic cone. The first master latch couples to the first fanout path and is configured to receive a first data input signal. The first fanout path comprises a plurality of output sinks, each coupled to the logic cone. The first behavioral model is modified to generate a second behavioral model describing the physical circuit in a second configuration. The second configuration comprises an error circuit and an abstract latch clone based on the first master latch. A configuration file is generated based on the second behavioral model. The configuration file comprises information representing a plurality of instantiated latch clones based on the abstract latch clone, each configured to couple to the first data input signal and to one or more output sinks of the plurality of output sinks. The second behavioral model and the configuration file are together configured for input to a synthesis tool. | 02-23-2012 |
20120066654 | STABILITY-DEPENDENT SPARE CELL INSERTION - Spare cells are placed in an IC design using stability values associated with logic cones of the design. A desired spare cell utilization rate is assigned to a cone based on its stability value, and an actual spare cell utilization rate for the cone bounding box is calculated. If the actual utilization rate is less than the desired utilization rate, additional spare cells are inserted as needed to attain the desired utilization rate. The stability value is provided by a logic or circuit designer, or derived from historical information regarding the logic cone in a previous design iteration. Spare cells are placed for each logic cone in the design until a global spare cell utilization target is exceeded. The spare cell placement method can be an integrated part of a placement directed synthesis which is followed by early mode padding and design routing. | 03-15-2012 |
20120266124 | Placement of Structured Nets - Mechanisms are provided for performing placement of cells in a design of a semiconductor device. An initial design of the semiconductor device is generated, the initial design comprising a first placement of cells. A preferred direction of placement associated with the cells is determined. The preferred direction is a direction along which spreading of the cells is preferred. A second design of the semiconductor device is generated by modifying the first placement of the cells to generate a second placement of cells, different from the first placement cells, based on the preferred direction of placement associated with the cells. | 10-18-2012 |
20120284676 | DECOUPLING CAPACITOR INSERTION USING HYPERGRAPH CONNECTIVITY ANALYSIS - Decoupling capacitors (dcaps) are placed in an IC design by assigning different dcap utilization rates to logic cones, applying the rates to corresponding dcap regions surrounding cells in the cones, identifying any overlap of regions from different logic cones, and inserting a dcap at the overlapping region having the highest dcap utilization rate. The best location for the dcap is computed using a hypergraph wherein the cells are edges and the regions are nodes. Any node that is dominated by another node is removed and its edge is extended to the dominating node. The dcap is inserted in the region having the most edges (the edges can be weighted). The process is repeated iteratively, updating the hypergraph by removing nodes connected to dcap location, and inserting the next dcap at a region corresponding to the node which then has the greatest number of connected edges. | 11-08-2012 |
20130014011 | RECORDING EVENTS IN A VIRTUAL WORLD - Systems, methods and articles of manufacture are disclosed for recording events occurring in a virtual world. In one embodiment, properties of events previously recorded and/or attended by a user may be identified. Recording criteria for the user may be derived from the identified properties. Upon identifying an event satisfying the recording criteria, the event may be recorded. The recorded event may be played back at the convenience of the user. | 01-10-2013 |
20130097573 | ALIGNMENT NET INSERTION FOR STRAIGHTENING THE DATAPATH IN A FORCE-DIRECTED PLACER - An automated method for aligning a critical datapath in an integrated circuit design inserts an artificial alignment net in the netlist which interconnects all cells in the bit stack of the datapath. The cells are placed using a wirelength optimization which assigns weights to wire sections based on the alignment direction. The rate of change of the alignment weighting value can vary during different stages of global placement. The invention is particularly suited for a force-directed placer which uses a linear system solver to obtain a globally optimum solution for placement of the cells having some overlap among the cells, and thereafter spreads the cells to reduce the overlap. Pseudo nets are also inserted which interconnect a cell and an expected location of the cell after spreading for that iteration. | 04-18-2013 |
20130205272 | ALIGNMENT NET INSERTION FOR STRAIGHTENING THE DATAPATH IN A FORCE-DIRECTED PLACER - An automated method for aligning a critical datapath in an integrated circuit design inserts an artificial alignment net in the netlist which interconnects all cells in the bit stack of the datapath. The cells are placed using a wirelength optimization which assigns weights to wire sections based on the alignment direction. The rate of change of the alignment weighting value can vary during different stages of global placement. The invention is particularly suited for a force-directed placer which uses a linear system solver to obtain a globally optimum solution for placement of the cells having some overlap among the cells, and thereafter spreads the cells to reduce the overlap. Pseudo nets are also inserted which interconnect a cell and an expected location of the cell after spreading for that iteration. | 08-08-2013 |
20130283225 | DATAPATH PLACEMENT USING TIERED ASSIGNMENT - Datapath placement defines tiers for placement sets of a cell cluster, assigns cells to the tiers constrained by the datapath width, and then orders cells within each tier. Clusters are identified using machine-learning based datapath extraction. Datapath width is determined by computing a size of a bounding box for cells in the cluster. Placement sets are identified using a breadth-first search beginning with input cells for the cluster. Tiers are initially defined using logic depth assignment. A cell may be assigned to a tier by pulling the cell from the next higher tier to fill an empty location or by pushing an excess cell into the next higher tier. Cells are ordered within each tier using greedy cell assignment according to a wirelength cost function. The datapath placement can be part of an iterative process which applies spreading constraints to the cluster based on computed congestion information. | 10-24-2013 |
20130326441 | MACHINE-LEARNING BASED DATAPATH EXTRACTION - A datapath extraction tool uses machine-learning models to selectively classify clusters of cells in an integrated circuit design as either datapath logic or non-datapath logic based on cluster features. A support vector machine and a neural network can be used to build compact and run-time efficient models. A cluster is classified as datapath if both the support vector machine and the neural network indicate that it is datapath-like. The cluster features may include automorphism generators for the cell clusters, or physical information based on the cell locations from a previous (e.g., global) placement, such as a ratio of a total cell area for a given cluster to a half-perimeter of a bounding box for the given cluster. | 12-05-2013 |
20140026110 | GENERATING AND SELECTING BIT-STACK CANDIDATES FROM A GRAPH USING DYNAMIC PROGRAMMING - Bit stacks of an integrated circuit design are identified in a netlist by analyzing cell clusters. Candidate bit stacks are generated for each cluster using cone tracing, and wirelength costs are calculated for the candidate bit stacks based on the cells' locations from a previous (e.g., global) placement. The bit stack partition having a minimum total wirelength cost is selected for the final bit stacks. The invention can find K bit stacks in a cell cluster having N input cells and M output cells, where K, N and M are all different. The method is advantageously made timing aware by weighting connections between cells using weights based on timing information. Once the final bit stacks have been identified, the information can be included in the netlist and passed to a datapath placer for optimized placement. | 01-23-2014 |
20140189630 | SOFT PIN INSERTION DURING PHYSICAL DESIGN - A netlist for an integrated circuit design is constrained by virtual or “soft” pins to control or stabilize the placement of logic such as an architectural logic path. One soft pin is inserted at a fixed location proximate an input net of the path and is interconnected with the input net, and another is inserted at a fixed location proximate the output net and is interconnected with the output net. Cell placement is then optimized while maintaining the virtual pins at their fixed locations. More than two virtual pins may be inserted to bound a cluster of logic. The virtual pins may lie along the input/output nets. Pseudo-net weights are assigned to pseudo-nets formed between a cell and the virtual pins, and the pseudo-net weight can be increased for each placement iteration. | 07-03-2014 |
20140372960 | MACHINE-LEARNING BASED DATAPATH EXTRACTION - A datapath extraction tool uses machine-learning models to selectively classify clusters of cells in an integrated circuit design as either datapath logic or non-datapath logic based on cluster features. A support vector machine and a neural network can be used to build compact and run-time efficient models. A cluster is classified as datapath if both the support vector machine and the neural network indicate that it is datapath-like. The cluster features may include automorphism generators for the cell clusters, or physical information based on the cell locations from a previous (e.g., global) placement, such as a ratio of a total cell area for a given cluster to a half-perimeter of a bounding box for the given cluster. | 12-18-2014 |
20150067625 | MACHINE-LEARNING BASED DATAPATH EXTRACTION - A datapath extraction tool uses machine-learning models to selectively classify clusters of cells in an integrated circuit design as either datapath logic or non-datapath logic based on cluster features. A support vector machine and a neural network can be used to build compact and run-time efficient models. A cluster is classified as datapath if both the support vector machine and the neural network indicate that it is datapath-like. The cluster features may include automorphism generators for the cell clusters, or physical information based on the cell locations from a previous (e.g., global) placement, such as a ratio of a total cell area for a given cluster to a half-perimeter of a bounding box for the given cluster. | 03-05-2015 |