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| 20120068241 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a memory device includes first and second fin type stacked structures each includes first to i-th memory strings (i is a natural number except 1) that are stacked in a first direction, the first and second fin type stacked structures which extend in a second direction and which are adjacent in a third direction, a first portion connected to one end in the second direction of the first fin type stacked structure, a width in the third direction of the first portion being greater than a width in the third direction of the first fin type stacked structure, and a second portion connected to one end in the second direction of the second fin type stacked structure, a width in the third direction of the second portion being greater than a width in the third direction of the second fin type stacked structure. | 03-22-2012 |
| 20120068254 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a memory device includes a semiconductor substrate, first, second, third and fourth fin-type stacked layer structures, each having memory strings stacked in a first direction perpendicular to a surface of the semiconductor substrate, and each extending to a second direction parallel to the surface of the semiconductor substrate, a first part connected to first ends in the second direction of the first and second fin-type stacked layer structures each other, a second part connected to first ends in the second direction of the third and fourth fin-type stacked layer structures each other, a third part connected to second ends in the second direction of the first and third fin-type stacked layer structures each other, and a fourth part connected to second ends in the second direction of the second and fourth fin-type stacked layer structures each other. | 03-22-2012 |
| 20120139030 | NONVOLATILE SEMICONDUCTOR MEMORY - According to one embodiment, a nonvolatile semiconductor memory includes first to n-th (n is a natural number not less than 2) semiconductor layers in a first direction and extend in a second direction, and the semiconductor layers having a stair case pattern in a first end of the second direction, a common semiconductor layer connected to the first to n-th semiconductor layers commonly in the first end of the second direction, first to n-th layer select transistors which are provided in order from the first electrode side between the first electrode and the first to n-th memory strings, and first to n-th impurity regions which make the i-th layer select transistor (i is one of 1 to n) a normally-on state in the first end of the second direction of the i-th semiconductor layer. | 06-07-2012 |
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| 20080251881 | SEMICONDUCTOR DEVICE WITH DOUBLE BARRIER FILM - A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has a bottom in the second barrier film. The bottom has a width greater than a trench made in the first insulation layer, as measured in a direction crossing the widthwise direction of the trench. The lower contact hole penetrates the first insulation layer and first barrier film, communicates with the first contact hole via the trench and is provided on the diffusion layer. The upper portion of the lower contact hole has the same width as the trench. The contact plug is provided in the upper contact hole and lower contact hole. | 10-16-2008 |
| 20090016108 | NONVOLATILE SEMICONDUCTOR MEMORY - A method of reading out data from nonvolatile semiconductor memory including the steps of applying a first voltage to a bit line contact; applying a second voltage to a source line contact, wherein the second voltage is substantially smaller than the first voltage; applying a third voltage gates of third and fourth select gate transistors, the third voltage configured to bring the third and fourth select gate transistors into conduction; applying a fourth voltage to gates of the plurality of memory cell transistors of a second memory cell unit, the fourth voltage configured to bring the plurality of memory cell transistors of the second memory cell unit into conduction or not, depending on the data that is stored in the memory cell unit; and applying a fifth voltage to gates of the plurality of memory cell transistors of a first memory cell unit, the fifth voltage configured to bring the plurality of memory cell transistors of the first memory cell unit into conduction; wherein the fifth voltage is bigger than the fourth voltage. | 01-15-2009 |
| 20090242960 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes a semiconductor substrate, a memory cell provided on the semiconductor substrate and having a stacked gate structure formed by sequentially stacking a tunnel insulation film, a charge storage layer, a block insulation film, and a control gate electrode, a first transistor having a first gate electrode provided on the semiconductor substrate via a gate insulation film, and a resistor element provided on the semiconductor substrate and formed of polysilicon. The control gate electrode is entirely formed of a silicide layer. An upper portion of the first gate electrode partially includes a silicide layer. | 10-01-2009 |
| 20100177546 | SEMICONDUCTOR DEVICE - A semiconductor device includes a memory cell array area, a peripheral circuit area on a periphery of the memory cell array area, and a boundary area having a specific width between the memory cell array area and the peripheral circuit area, the memory cell array area including a cell area including nonvolatile semiconductor memory cells, linear wirings extending from inside of the cell area to an area outside the cell area, and lower layer wirings in a lower layer than the linear wirings in the boundary area and electrically connected to the linear wirings, and wiring widths of the lower layer wirings being larger than widths of the linear wirings, the peripheral circuit area including a patterns electrically connected to the linear wirings via the lower layer wirings, the boundary area failing to be provided with the linear wirings and a wiring in same layer as the linear wirings. | 07-15-2010 |
| 20110267867 | SEMICONDUCTOR DEVICE - A semiconductor device includes a memory cell array area, a peripheral circuit area on a periphery of the memory cell array area, and a boundary area having a specific width between the memory cell array area and the peripheral circuit area, the memory cell array area including a cell area including nonvolatile semiconductor memory cells, linear wirings extending from inside of the cell area to an area outside the cell area, and lower layer wirings in a lower layer than the linear wirings in the boundary area and electrically connected to the linear wirings, and wiring widths of the lower layer wirings being larger than widths of the linear wirings, the peripheral circuit area including a patterns electrically connected to the linear wirings via the lower layer wirings, the boundary area failing to be provided with the linear wirings and a wiring in same layer as the linear wirings. | 11-03-2011 |
| 20120135356 | SEMICONDUCTOR DEVICE - A semiconductor device includes a memory cell array area, a peripheral circuit area on a periphery of the memory cell array area, and a boundary area having a specific width between the memory cell array area and the peripheral circuit area, the memory cell array area including a cell area including nonvolatile semiconductor memory cells, linear wirings extending from inside of the cell area to an area outside the cell area, and lower layer wirings in a lower layer than the linear wirings in the boundary area and electrically connected to the linear wirings, and wiring widths of the lower layer wirings being larger than widths of the linear wirings, the peripheral circuit area including a patterns electrically connected to the linear wirings via the lower layer wirings, the boundary area failing to be provided with the linear wirings and a wiring in same layer as the linear wirings. | 05-31-2012 |
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| 20080245553 | INTERCONNECTION, ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE - An interconnection includes a bundle of conductive members, each of the conductive members being made of carbon nanotube having an end connected to a first conductive film, and another end connected to a second conductive film separated from the first conductive film; and carbon particles each having a diamond crystal structure, dispersed between the conductive members. | 10-09-2008 |
| 20110050080 | ELECTRON EMISSION ELEMENT - According to the embodiment, an electron emission element includes a conductive substrate, a first diamond layer of a first conductivity type formed on the conductive substrate, and a second diamond layer of the first conductivity type formed on the first diamond layer. Thereby, it becomes possible to provide the electron emission element having a high electron emission amount and a high current density even in a low electric field at low temperature and the electron emission apparatus using this electron emission element. | 03-03-2011 |
| 20110057322 | CARBON NANOTUBE INTERCONNECT AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a carbon nanotube interconnect includes a first interconnection layer, an interlayer dielectric film, a second interconnection layer, a contact hole, a plurality of carbon nanotubes and a film. The interlayer dielectric film is formed on the first interconnection layer. The second interconnection layer is formed on the interlayer dielectric film. The contact hole is formed in the interlayer dielectric film between the first interconnection layer and the second interconnection layer. The carbon nanotubes are formed in the contact hole. The carbon nanotubes have a first end connected to the first interconnection layer and a second end connected to the second interconnection layer. The film is formed between the interlayer dielectric film and the second interconnection layer. The film has a portion filled between the second ends of the carbon nanotubes. | 03-10-2011 |
| 20110233779 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes an interlayer insulation film provided on a substrate including a Cu wiring, a via hole formed in the interlayer insulation film on the Cu wiring, a first metal film selectively formed on the Cu wiring in the via hole, functioning as a barrier to the Cu wiring, and functioning as a promoter of carbon nanotube growth, a second metal film formed at least on the first metal film in the via hole, and functioning as a catalyst of the carbon nanotube growth, and carbon nanotubes buried in the via hole in which the first metal film and the second metal film are formed. | 09-29-2011 |
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| 20090065476 | METHOD FOR MANUFACTURING LIQUID DISCHARGE HEAD - A method for manufacturing a substrate for a liquid discharge head having a silicon substrate provided with a supply port of a liquid comprises steps of preparing a substrate which is provided with a passive film on one side face thereof, has a first recess and a second recess provided therein so as to penetrate from the one side face into the inner part through the passive film, wherein the recesses satisfy a relation of a×tan 54.7 degrees≦d, when a is defined as a distance between the first recess and the second recess, and d is defined as a depth of the second recess, and forming the supply port by anisotropically etching the crystal from the one side face. | 03-12-2009 |
| 20090315953 | LIQUID EJECTION HEAD AND METHOD OF MANUFACTURING THE SAME - Provided is a method of manufacturing a liquid ejection head having an element which generates energy utilized for ejecting liquid and an electrode layer electrically connected the element. The method includes the steps of: providing an electrode layer on a substrate, a width of one portion of the electrode layer being smaller than that of another portion near the one portion; providing a resist layer on a part of the electrode layer by any one of a screen printing method and a dispense method in such a manner that an end of the resist layer is positioned at the one portion; providing another layer on another part excluding the part of the electrode layer by utilizing the resist layer as a mask; and removing the resist layer. | 12-24-2009 |
| 20090315955 | LIQUID EJECTION HEAD - It is an objective of the present invention to provide an ink jet printing head substrate by which a high adhesion can be obtained between an electrode layer and a nozzle formation member and the corrosion or electrolysis for example of a electrode due to the contact between the electrode and ink can be reduced. To realize this, the present invention includes: an electrode layer for supplying power to a heat-generating portion that is provided on a substrate and that generates thermal energy for ejecting ink; and a resin layer provided on the electrode layer via a nickel-containing layer. The electrode layer includes precious metal as a main component. The nickel-containing layer consists of gold-nickel alloy containing nickel. | 12-24-2009 |
| 20090315958 | LIQUID EJECTION HEAD - Provided is a liquid ejection head having a structure in which an organic resinous member is formed in contact with a substrate. The substrate includes heat generators for generating heat energy used to eject ink, when being energized, and a metallic line portion for energizing the heat generators. The organic resinous member is provided with ejection openings corresponding to the heat generators. In the liquid ejection head, the substrate and the organic resinous member have an improved adhesion therebetween, and are prevented from being separated from each other. To improve the adhesion, the metallic line portion is cut so that no line portion exists under an end part of the organic resinous member (nozzle formation member). Then, two members of the line portion thus cut are connected to each other through a roundabout line formed under an insulating layer which has a good adhesion to the organic resin. | 12-24-2009 |
