Patent application number | Description | Published |
20090314326 | PHOTOVOLTAIC MODULE - Embodiments relate to an apparatus for generating electricity from solar energy, said apparatus having a base substrate; one or more photovoltaic strips arranged over said base substrate, wherein spaces are formed in between adjacent photovoltaic strips; a plurality of optical vees for concentrating solar energy over said photovoltaic strips, said optical vees being placed in said spaces between said photovoltaic strips, said optical vees comprising a reflective layer or surface, such that rays incident on said reflective layer or surface are reflected towards said photovoltaic strips; and a transparent member positioned over said optical vees, wherein said base substrate, said photovoltaic strips, said optical vees and said transparent member form said apparatus in an integrated manner. Other embodiments include systems for generating electricity using the photovoltaic module. Yet other embodiments relate to methods of manufacturing the photovoltaic module and systems for generating electricity using the photovoltaic module. | 12-24-2009 |
20090314327 | PHOTOVOLTAIC MODULE - Embodiments include an apparatus for generating electricity from solar energy, said apparatus comprising a base substrate for; a plurality of connectors attached to said base substrate, wherein connecting spaces are formed between adjacent said connectors; one or more photovoltaic strips arranged in said connecting spaces over said base substrate; a plurality of optical vees for concentrating solar energy over said photovoltaic strips, said optical vees being connected to said base substrate through said connectors, said optical vees comprising a reflective layer or surface, such that rays incident on said reflective layer or surface are reflected towards said photovoltaic strips; and a transparent member positioned over said optical vees, wherein said base substrate, said connectors, said photovoltaic strips, said optical vees and said transparent member form said apparatus in an integrated manner. Other embodiments include systems for generating electricity using the photovoltaic module. Yet other embodiments relate to methods of manufacturing the photovoltaic module and systems for generating electricity using the photovoltaic module. | 12-24-2009 |
20090314328 | PHOTOVOLTAIC MODULE - Embodiments include a photovoltaic module for generating electricity from solar energy, said photovoltaic module having a base substrate; one or more photovoltaic strips arranged over said base substrate, wherein spaces are formed in between adjacent photovoltaic strips; a plurality of optical vees located in the spaces between said photovoltaic strips, such that one or more cavities are formed between said optical vees; and a polymeric material in a fluid state is introduced over the photovoltaic strips and the optical vees, such that the polymeric material fills the cavities between the optical vees and forms a plurality of molded concentrating elements for concentrating solar energy over the photovoltaic strips. Other embodiments include systems for generating electricity using the photovoltaic module. Yet other embodiments relate to methods of manufacturing the photovoltaic module and systems for generating electricity using the photovoltaic module. | 12-24-2009 |
20090314329 | PHOTOVOLTAIC MODULE - Embodiments relate to a photovoltaic module for generating electricity from solar energy, said photovoltaic module comprising a base substrate; one or more photovoltaic strips arranged over said base substrate, wherein spaces are formed in between adjacent photovoltaic strips; a plurality of optical vees placed in the spaces between said photovoltaic strips, such that one or more cavities are formed between said optical vees; and a plurality of pre-molded concentrating elements are placed on the photovoltaic strips, and re-molded over the photovoltaic strips to form re-molded concentrating elements, wherein said concentrating elements take the shape of said cavities. Other embodiments include systems for generating electricity using the photovoltaic module. Yet other embodiments relate to methods of manufacturing the photovoltaic module and systems for generating electricity using the photovoltaic module | 12-24-2009 |
20090314330 | PHOTOVOLTAIC MODULE - Methods and systems for fabricating a photovoltaic module are provided. One or more stiffeners are integrated with a base substrate for stiffening the base substrate. One or more photovoltaic strips are arranged over the base substrate, such that spaces are formed between adjacent photovoltaic strips. The photovoltaic strips are connected through one or more conductors in a predefined manner. A plurality of optical vees are placed in the spaces between the photovoltaic strips for concentrating solar energy over the photovoltaic strips. | 12-24-2009 |
20090314334 | ELECTRONIC SUBSTRATE FOR A PHOTOVOLTAIC MODULE - Methods and systems for fabricating a photovoltaic module are provided. One or more conducting pads are formed over a base of an electronic substrate, such that pad spaces are created between adjacent conducting pads. The electronic substrate includes a plurality of path options, and one or more bond pads. The path options are embedded in the base. The bond pads are formed over the base. One or more photovoltaic strips are arranged over the conducting pads. The bond pads provide an interface to connect photovoltaic strips to at least one of the path options. The photovoltaic strips are connected to the bond pads through one or more connectors in series and/or parallel. A plurality of optical vees is placed in the pad spaces between the conductive pads for concentrating solar energy over the photovoltaic strips. | 12-24-2009 |
Patent application number | Description | Published |
20090103622 | METHOD AND SYSTEM FOR DETERMINING A MACROBLOCK PARTITION FOR DATA TRANSCODING - A system and corresponding method determines a macroblock partition to transcode digital data from a first video standard to a second video standard with any spatial resolution. The system includes a processing module and an encoding module. The processing module processes digital data to determine a macroblock partition. The encoding module is coupled to the processing module for encoding the digital data based on the macroblock partition. The system is further coupled to a decoding module for receiving the digital data. The method determines the partition of a macroblock for transcoding digital data with any spatial resolution and without any motion estimation. | 04-23-2009 |
20090265739 | METHOD AND SYSTEM FOR CHANNEL SELECTION IN A DIGITAL BROADCAST RECEPTION TERMINAL - The present invention discloses a system and method for channel selection in a digital broadcast reception terminal. The system tunes to different frequencies and generates visual clips corresponding to a plurality of channels in a frequency band. Visual clips of multiple channels are simultaneously displayed on a display screen which provides the user an easy way to select a desired program. | 10-22-2009 |
20100158108 | SYSTEM AND METHOD FOR VIDEO ENCODING - An embodiment of the present disclosure relates to system comprises an encoding device. Said encoding device comprises a compression unit, a quantizer, a bit estimator, a bit rate encoder and a variable length encoder. An embodiment also is a method of encoding. Said method estimates a number of bits to encode a macroblock after compressing the data stream. Then the estimated bit encoded by a bit rate encoder and further quantized by the quantizer to get the final encoded bit stream. The number of bits required to encode a macroblock is estimated after the quantization process and before the encoding process. The macroblock bit estimator estimates the number of bits required to encode a particular macroblock depending on the quantized AC coefficients of that macroblock and the quantized AC coefficients of the neighboring frames normalized at a macroblock level. | 06-24-2010 |
20110150351 | PARALLELIZATION OF VARIABLE LENGTH DECODING - Parallelization of decoding of a data stream encoded with a variable length code includes determining one or more markers, each of which indicates a position within the encoded data stream. The determined markers are included into the encoded data stream together with the encoded data. At the decoder side, the markers are parsed from the encoded data stream and based on the extracted markers. The encoded data is separated into partitions, which are decoded separately and in parallel. | 06-23-2011 |
20110291642 | POWER MEASUREMENT CIRCUIT - A system for power measurement in an electronic device includes a sensing unit, an analog-to-digital converter (ADC) and a controller. The sensing unit senses voltage across a power source and modulates a carrier signal based on the sensed voltage. The ADC converts a combination of the modulated carrier signal and audio signals received by the electronic device to generate a digitized combined signal and provides the digitized combined signal to the controller. The controller separates digitized modulated carrier signal and digitized audio signals. The digitized modulated carrier signal is demodulated to generate an output signal that provides a measure of the power consumed by the electronic device. | 12-01-2011 |
20120044226 | IMAGE PROCESSING ARRANGEMENT - An image processing arrangement includes an input to receive an indicator of a power characteristic related to an image processing arrangement and an image processor to process an image based on the indicator of the power characteristic. | 02-23-2012 |
20120169378 | DIFFERENTIAL DATA SENSING - A first sensing circuit has input terminals coupled to a true differential signal line and a complementary differential signal line. A second sensing circuit also has input terminals coupled to said true signal and said complementary signal. Each sensing circuit has a true signal sensing path and a complementary signal sensing path. The first sensing circuit has an imbalance that is biased towards the complementary signal sensing path, while the second sensing circuit has an imbalance that is biased towards the true signal sensing path. Outputs from the first and second sensing circuits are processed by a logic circuit producing an output signal that is indicative of whether there a sufficient differential signal for sensing has been developed between the true differential signal line and the complementary differential signal line. | 07-05-2012 |
20130169360 | APPARATUS - According to an embodiment, an apparatus includes: a first node configured to receive a data input signal of a data latch; a second node configured to receive a data output signal of the data latch; process and hold circuitry configured to process a difference between a value of the data input signal received at the first node and a value of the data output signal received at the second node and hold respective values at the first and second nodes responsive to the difference; and comparison circuitry configured to compare the value held at the first node and a value of the data output signal of the data latch; wherein the process and hold circuitry is configured to be biased toward the signal received at one of the first node and the second node. | 07-04-2013 |
20130170306 | MEMORY ARCHITECTURE AND DESIGN METHODOLOGY WITH ADAPTIVE READ - An embodiment of a sense amplifier includes a sense circuit and a monitor circuit. The sense circuit is configured to convert a first signal that corresponds to data stored in a memory cell into a second signal that corresponds to the data, and the monitor circuit is configured to indicate a reliability of the second signal. The monitor circuit allows, for example, adjusting a parameter of a memory in which the memory cell is disposed to increase the read accuracy, and may also allow recognizing and correcting an error due to an invalid second signal. | 07-04-2013 |
20130330013 | PARALLELIZATION OF VARIABLE LENGTH DECODING - Parallelization of decoding of a data stream encoded with a variable length code includes determining one or more markers, each of which indicates a position within the encoded data stream. The determined markers are included into the encoded data stream together with the encoded data. At the decoder side, the markers are parsed from the encoded data stream and based on the extracted markers. The encoded data is separated into partitions, which are decoded separately and in parallel. | 12-12-2013 |
20140047285 | MEMORY MANAGER - An embodiment of a manager includes at least one input node configured to receive information regarding a region of an integrated circuit, and a determiner configured to determine, in response to the information, a likelihood that the region will cause an error. For example, the region may include a memory, and contents of the memory may be transferred to another, more reliable memory, if the likelihood that the memory will cause an error in the data that it stores equals or exceeds a likelihood threshold. | 02-13-2014 |
20140055438 | IMAGE PROCESSING ARRANGEMENT ILLUMINATING REGIONS OF AN IMAGE BASED ON MOTION - An image processing arrangement includes an input to receive an indicator of a power characteristic related to an image processing arrangement and an image processor to process an image based on the indicator of the power characteristic. | 02-27-2014 |
20140062460 | POWER MEASUREMENT CIRCUIT - A system for power measurement in an electronic device includes a sensing unit, an analog-to-digital converter (ADC) and a controller. The sensing unit senses voltage across a power source and modulates a carrier signal based on the sensed voltage. The ADC converts a combination of the modulated carrier signal and audio signals received by the electronic device to generate a digitized combined signal and provides the digitized combined signal to the controller. The controller separates digitized modulated carrier signal and digitized audio signals. The digitized modulated carrier signal is demodulated to generate an output signal that provides a measure of the power consumed by the electronic device. | 03-06-2014 |
20140074979 | WEB BASED SMART SENSOR NETWORK TRACKING AND MONITORING SYSTEM - A wireless sensor network including a plurality of Smart Sensors coupled to a wide area network such as the Internet via a Wireless Sensor Coordinator. Each wireless sensor network comprises a plurality of Smart Sensors, each operable to measure one or more physical quantities. Each wireless sensor communicates the measured data to a Wireless Sensor Coordinator which then stores the collected data in memory. The Wireless Sensor Coordinator further includes a web server operable to post a web site on a network that is accessible by a common web browser. Upon receiving a request for sensed data via the web site, the Wireless Sensor Coordinator retrieves the appropriate measured and stored data and converts it into HTML format pages which are then posted on the web site for review by the requestor. | 03-13-2014 |
Patent application number | Description | Published |
20150113488 | CONGESTION ESTIMATION TECHNIQUES AT PRE-SYNTHESIS STAGE - A method analyzes RTL code to determine congestion of a logic design without completing a synthesis phase of a chip design process. The method can include receiving RTL code, and identifying a statement in the RTL code. The method can include determining that the statement in the RTL code corresponds to a structured device group in a component library, wherein the structured device group includes logic devices configured to occupy an area in a predefined spatial arrangement and with predetermined connectivity between the logic devices. The method can include determining congestion associated with the structured device group by performing operations including determining a congestion figure. The method can also include providing, based on the congestion figure, an indication of the congestion associated with the structured device group. | 04-23-2015 |
20150113490 | CONGESTION ESTIMATION TECHNIQUES AT PRE-SYNTHESIS STAGE - An apparatus includes a memory device that includes instructions for analyzing RTL code to determine congestion of a logic design without completing a synthesis phase of a chip design process. The instructions can include receiving RTL code, and identifying a statement in the RTL code. The instructions can include determining that the statement in the RTL code corresponds to a structured device group in a component library, wherein the structured device group includes logic devices configured to occupy an area in a predefined spatial arrangement and with predetermined connectivity between the logic devices. The instructions can include determining congestion associated with the structured device group by performing operations including determining a congestion figure. The instructions can also include providing, based on the congestion figure, an indication of the congestion associated with the structured device group. | 04-23-2015 |
20150234948 | BOUNDARY BASED POWER GUIDANCE FOR PHYSICAL SYNTHESIS - A method and system to obtain a physical design of an integrated circuit from a logical design are described. The method includes performing a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget. The method also includes computing power assertions, performing a re-synthesis using the timing constraints and the power assertions to obtain a new physical design, comparing the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design, and reducing a weighting of the power assertions relative to the timing constraints based on the degradation. The executing the performing the re-synthesis, the comparing, and the reducing are done iteratively until the degradation is below a threshold value. | 08-20-2015 |
20150234949 | BOUNDARY BASED POWER GUIDANCE FOR PHYSICAL SYNTHESIS - A method and system to obtain a physical design of an integrated circuit from a logical design are described. The system includes a memory device to store a logical design, and a processor to execute a synthesis engine. The processor performs a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget, computes power assertions, performs a re-synthesis using the timing constraints and the power assertions to obtain a new physical design, compares the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design, reduces a weighting of the power assertions relative to the timing constraints based on the degradation, and iteratively performs the re-synthesis, compares the new physical design with the baseline physical design, and reduces the weighting until the degradation is below a threshold value. | 08-20-2015 |
20150242559 | PLACEMENT AWARE FUNCTIONAL ENGINEERING CHANGE ORDER EXTRACTION - A computer implemented method for designing an integrated circuit includes receiving a netlist; receiving physical layout information related to an integrated circuit based on the on the netlist; receiving an engineering change order (ECO) that changes at least one logical component of the physical layout; forming two or more possible solutions to achieve the ECO; ranking the two or more possible solutions based on two or more factors; and selecting the highest ranked solution. | 08-27-2015 |
20150334022 | VIRTUAL SUB-NET BASED ROUTING - A method and system to route connections of sub-networks in a design block of an integrated circuit and a computer program product are described. The system includes a memory device to store instructions to route the connections of the sub-networks, and a processor to execute the instructions to determine a baseline route for each of the connections of each of the sub-networks, identify noise critical sub-networks in the integrated circuit design based on congestion, set a mean threshold length (MTL), segment the connections of the noise critical sub-networks based on the MTL, and re-route the baseline route based on segmenting. The MTL indicates a maximum length of each segment of each connection, each segment includes a different wirecode than an adjacent segment, and the wirecode defines a width, metal layer, and spacing for the segment. | 11-19-2015 |
20150347640 | PHYSICAL AWARE TECHNOLOGY MAPPING IN SYNTHESIS - A method of performing physical aware technology mapping in a logic synthesis phase of design of an integrated circuit and a system to perform physical aware technology mapping are described. The method includes subdividing a core area representing a sub-block of the integrated circuit into equal-sized grids. The method also includes determining a location of each of one or more latches in the logic design based on an algorithm, determining a location of each of one or more combinational logic gates in the logic design based on the locations of the one or more latches, and obtaining the technology mapping based on the locations of the one or more latches, one or more input ports, or one or more output ports, the locations of the one or more combinational logic gates, and associated path delays. | 12-03-2015 |
20150347643 | PHYSICAL AWARE TECHNOLOGY MAPPING IN SYNTHESIS - A method of performing physical aware technology mapping in a logic synthesis phase of design of an integrated circuit and a system to perform physical aware technology mapping are described. The system includes a memory device to store a logic design of the integrated circuit, and a processor to subdivide a core area representing a sub-block of the integrated circuit into equal-sized grids, the core area including one or more input ports and one or more output ports, to determine a location of each latch in a logic design based on an algorithm, to determine a location of each combinational logic gate in the logic design, and to obtain the technology mapping based on the locations of the one or more latches, the locations of the one or more combinational logic gates, and associated path delays. | 12-03-2015 |
20150347661 | CONGESTION AWARE LAYER PROMOTION - Embodiments relate to managing layer promotion of interconnects in the routing phase of integrated circuit design. An aspect includes reducing the set of candidate interconnects for layer promotion based on resource availability. A method of managing includes identifying a set of candidate interconnects for the layer promotion, scoring and sorting the set of candidate interconnects according to a respective score, thereby establishing a respective rank, and assessing routing demand and resource availability based on promoting the set of candidate interconnects. The method also includes managing the set of candidate interconnects based on the respective rank and the assessing, the assessing and the managing being done iteratively and the managing including, in at least one iteration, generating a second set of candidate interconnects based on reducing the set of candidate interconnects. | 12-03-2015 |
20150347662 | CONGESTION AWARE LAYER PROMOTION - Embodiments relate to managing layer promotion of interconnects in the routing phase of integrated circuit design. An aspect includes a system to manage layer promotion in a routing phase of integrated circuit design. The system includes a memory device to store instructions, and a processor to execute the instructions to identify a set of candidate interconnects for layer promotion, score and sort the set of candidate interconnects according to a respective score to thereby establish a respective rank, assess routing demand and resource availability based on layer promotion of the set of candidate interconnects, and manage the set of candidate interconnects based on the respective rank and the resource availability, the processor assessing the routing demand and resource availability and managing the set of candidate interconnects iteratively, wherein the processor, in at least one iteration, generates a second set of candidate interconnects by reducing the set of candidate interconnects. | 12-03-2015 |
20160042098 | BOUNDARY BASED POWER GUIDANCE FOR PHYSICAL SYNTHESIS - A method and system to obtain a physical design of an integrated circuit from a logical design are described. The method includes performing a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget. The method also includes computing power assertions, performing a re-synthesis using the timing constraints and the power assertions to obtain a new physical design, comparing the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design, and reducing a weighting of the power assertions relative to the timing constraints based on the degradation. The executing the performing the re-synthesis, the comparing, and the reducing are done iteratively until the degradation is below a threshold value. | 02-11-2016 |
20160070845 | CRITICAL REGION IDENTIFICATION - A method and system to identify a region of a design block of an integrated circuit for redesign are described. The method includes dividing the design block into grids, each of the grids including a corresponding number of logic elements. The method also includes filtering each of the grids based on a specified criteria, the filtering including determining a number (B) of the corresponding logic elements among a total number (A) of the logic elements in each grid that meet the specified criteria. The region is a set of two or more of the grids based on a result of the filtering. | 03-10-2016 |
20160070849 | CRITICAL REGION IDENTIFICATION - A method and system to identify a region of a design block of an integrated circuit for redesign are described. The method includes dividing the design block into grids, each of the grids including a corresponding number of logic elements. The method also includes filtering each of the grids based on a specified criteria, the filtering including determining a number (B) of the corresponding logic elements among a total number (A) of the logic elements in each grid that meet the specified criteria. The region is a set of two or more of the grids based on a result of the filtering. | 03-10-2016 |
20160098497 | BOUNDARY BASED POWER GUIDANCE FOR PHYSICAL SYNTHESIS - A method and system to obtain a physical design of an integrated circuit from a logical design are described. The system includes a memory device to store a logical design, and a processor to execute a synthesis engine. The processor performs a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget, computes power assertions, performs a re-synthesis using the timing constraints and the power assertions to obtain a new physical design, compares the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design, reduces a weighting of the power assertions relative to the timing constraints based on the degradation, and iteratively performs the re-synthesis, compares the new physical design with the baseline physical design, and reduces the weighting until the degradation is below a threshold value. | 04-07-2016 |