Patent application number | Description | Published |
20110131581 | Scheduling Virtual Interfaces - A mechanism is provided for scheduling virtual interfaces having at least one virtual interface scheduler, a virtual interface context cache and a pipeline with a number of processing units. The virtual interface scheduler is configured to send a lock request for a respective virtual interface to the virtual interface context cache. The virtual interface context cache is configured to lock a virtual interface context of the respective virtual interface and to send a lock token to the virtual interface scheduler in dependence on said lock request. The virtual interface context cache configured to hold a current lock token for the respective virtual interface context and to unlock the virtual interface context, if a lock token of an unlock request received from the pipeline matches the held current lock token. | 06-02-2011 |
20120290754 | Scheduling Virtual Interfaces - A mechanism is provided for scheduling virtual interfaces having at least one virtual interface scheduler, a virtual interface context cache and a pipeline with a number of processing units. The virtual interface scheduler is configured to send a lock request for a respective virtual interface to the virtual interface context cache. The virtual interface context cache is configured to lock a virtual interface context of the respective virtual interface and to send a lock token to the virtual interface scheduler in dependence on said lock request. The virtual interface context cache configured to hold a current lock token for the respective virtual interface context and to unlock the virtual interface context, if a lock token of an unlock request received from the pipeline matches the held current lock token. | 11-15-2012 |
20130124786 | MEMORY MODULE AND MEMORY CONTROLLER FOR CONTROLLING A MEMORY MODULE - The memory module having a plurality of memory chips and a plurality of connections for connecting the memory module to a processor. At least part of the connections is configurable to be grouped into N sets of address and control connections for N separatively controllable groups of memory chips of the plurality of memory chips (N≧2). | 05-16-2013 |
20130198455 | CACHE MEMORY GARBAGE COLLECTOR - A method for managing objects stored in a cache memory of a processing unit. The cache memory includes a set of entries corresponding to an object. The method includes: checking, for each entry of at least a subset of entries of the set of entries of the cache memory, whether an object corresponding to each entry includes one or more references to one or more other objects stored in the cache memory and storing the references; determining among the objects stored in the cache memory, which objects are not referenced by other objects, based on the stored references; marking entries as checked to distinguish entries corresponding to objects determined as being not referenced from other entries of the checked entries, and casting out, according to the marking, entries corresponding to objects determined as being not referenced. | 08-01-2013 |
20140095716 | MAXIMIZING RESOURCES IN A MULTI-APPLICATION PROCESSING ENVIRONEMENT - Aspects of the present invention provide a solution for maximizing server site resources in a server network. In an embodiment, an application signature is collected for an application. This application signature includes a representation of operating characteristics of the application. The application signature is compared with application signatures collected from other applications in the server network. Based on the comparison, the application is assigned for execution to a server site that hosts a group of applications that have similar application signatures to that of the application. | 04-03-2014 |
20140095718 | MAXIMIZING RESOURCES IN A MULTI-APPLICATION PROCESSING ENVIRONMENT - Aspects of the present invention provide a solution for maximizing server site resources in a server network. In an embodiment, an application signature is collected for an application. This application signature includes a representation of operating characteristics of the application. The application signature is compared with application signatures collected from other applications in the server network. Based on the comparison, the application is assigned for execution to a server site that hosts a group of applications that have similar application signatures to that of the application. | 04-03-2014 |
Patent application number | Description | Published |
20100042787 | CACHE INJECTION DIRECTING TOOL - A method for directing cache injection based on actual system load may include providing a snooping-based fabric having two or more bus-coupled units. At least one of the bus-coupled units may be configured as an injection unit for directing cache injection. A snoop request may be transmitted from the injection unit to one or more destination units of the other bus-coupled unit. The snoop request may include an identification value having a function identifier. The function identifier may identify a destination function for the cache injection, where the destination function is configured to run on the destination unit. A snoop response may be transmitted from the destination unit to the injection unit in response to the snoop request. The snoop response may include a function response value indicating whether the function identifier matches a function indication of a snoop register for the destination unit. | 02-18-2010 |
20120303948 | ADDRESS TRANSLATION UNIT, DEVICE AND METHOD FOR REMOTE DIRECT MEMORY ACCESS OF A MEMORY - An address translation unit for Remote Direct Memory Access (RDMA) of a memory of a processor is provided. The address translation unit comprises an address translator and a signer. The address translator is configured to translate a received virtual address in a real address of the memory. The signer is configured to cryptographically sign the real address. | 11-29-2012 |
20130019108 | ADDRESS TRANSLATION UNIT, DEVICE AND METHOD FOR REMOTE DIRECT MEMORY ACCESS OF A MEMORY - A method for Remote Direct Memory Access (RDMA) of a memory of a processor. An address translation unit comprises an address translator and a signer. The address translator is configured to translate a received virtual address in a real address of the memory. The signer is configured to cryptographically sign the real address. | 01-17-2013 |
20130151783 | INTERFACE AND METHOD FOR INTER-THREAD COMMUNICATION - The interface for inter-thread communication between a plurality of threads including a number of producer threads for producing data objects and a number of consumer threads for consuming the produced data objects includes a specifier and a provider. The specifier is configured to specify a certain relationship between a certain producer thread of the number of producer threads which is adapted to produce a certain data object and a consumer thread of the number of consumer threads which is adapted to consume the produced certain data object. Further, the provider is configured to provide direct cache line injection of a cache line of the produced certain data object to a cache allocated to the certain consumer thread related to the certain producer thread by the specified certain relationship. | 06-13-2013 |
20140156945 | MULTI-STAGE TRANSLATION OF PREFETCH REQUESTS - A device for multi-stage translation of prefetch requests includes a prefetch queue for providing queued prefetch requests, each of the queued prefetch requests including N different control entries; N serial-connected translation stages for the translation of N control entries of one of the queued prefetch requests into a translated prefetch request, wherein a translation in a i-th translation stage is dependent on a translation in a (i−1)-th translation stage, i ε [1, . . . ,N]; and a prefetch issuer which is configured to control an index for each of the N different control entries in the prefetch queue and to issue a prefetch of the indexed control entry of the N different control entries for the highest non-stalled translation stage. | 06-05-2014 |
Patent application number | Description | Published |
20090141630 | METHOD FOR MONITORING DATA CONGESTION IN A COMPUTER NETWORK WITH MULTIPLE NODES AND METHOD FOR CONTROLLING DATA TRANSMISSION IN THE COMPUTER NETWORK - A method for monitoring data congestion in a computer network with multiple nodes and for controlling data transmission in the computer network. The method includes generating a congestion notification by the node which detects a data congestion and transmitting the congestion notification to the data source which is involved in the data congestion. The method also includes generating in the data source a congestion value which indicates how severe the data congestion is, and storing in a worst case array of the data source those congestion values which indicate the most severe data congestions. | 06-04-2009 |
20090144505 | Memory Device - The present invention relates to a memory device, in particular, to a memory device comprising a cache memory with a predetermined amount of cache sets, each cache set comprising a predetermined amount of cache lines. Each cache line is operable to indicate a cache data injection into the particular cache line triggered by a bus-actor. | 06-04-2009 |
20130007375 | DEVICE AND METHOD FOR EXCHANGING DATA BETWEEN MEMORY CONTROLLERS - A device with an interconnect having a plurality of memory controllers for connecting the plurality of memory controllers. Each memory controller of the plurality of memory controllers is coupled to an allocated memory for storing data. Further, each memory controller of the plurality of memory controllers has one accelerator of a plurality of accelerators for mutually exchanging data over the interconnect. | 01-03-2013 |
20130007398 | DEVICE AND METHOD FOR EXCHANGING DATA BETWEEN MEMORY CONTROLLERS - A device with an interconnect having a plurality of memory controllers for connecting the plurality of memory controllers. Each memory controller of the plurality of memory controllers is coupled to an allocated memory for storing data. Further, each memory controller of the plurality of memory controllers has one accelerator of a plurality of accelerators for mutually exchanging data over the interconnect. | 01-03-2013 |