Rylov, US
German Rylov, Poway, CA US
Patent application number | Description | Published |
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20090080476 | Immersion lithography laser light source with pulse stretcher - An apparatus and method which may comprise a pulsed gas discharge laser which may comprise a seed laser portion; an amplifier portion receiving the seed laser output and amplifying the optical intensity of each seed pulse; a pulse stretcher which may comprise: a first beam splitter operatively connected with the first delay path and a second pulse stretcher operatively connected with the second delay path; a first optical delay path tower containing the first beam splitter; a second optical delay path tower containing the second beam splitter; one of the first and second optical delay paths may comprise: a plurality of mirrors defining the respective optical delay path including mirrors located in the first tower and in the second tower; the other of the first and second optical delay paths may comprise: a plurality of mirrors defining the respective optical delay path including mirrors only in one of the first tower and the second tower. | 03-26-2009 |
20100074295 | Immersion lithography laser light source with pulse stretcher - An apparatus and method are disclosed which may comprise a pulsed gas discharge laser lithography light source which may comprise a seed laser portion providing a seed laser output light beam of seed pulses; an amplifier portion receiving the seed laser output light beam and amplifying the optical intensity of each seed pulse to provide a high power laser system output light beam of output pulses; the amplifier portion may comprise a ring power amplifier comprising amplifier portion injection optics comprising at least one beam expanding prism, a beam reverser and an input/output coupler; the beam expansion optics and the output coupler may be mounted on an optics assembly with the beam expansion optics rigidly mounted with respect to the optics assembly and the input/output coupler mounted for relative movement with respect to the optics assembly for optical alignment purposes. | 03-25-2010 |
German E. Rylov, Poway, CA US
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20100097704 | Line narrowing module - An apparatus is disclosed which may comprise a grating receiving light, a first prism moveable to coarsely select an angle of incidence of the light on the grating, and a second prism moveable to finely select an angle of incidence of the light on the grating. In one application, the apparatus may be used as a line narrowing module for a laser light source. | 04-22-2010 |
20110194580 | Line Narrowing Module - An apparatus is disclosed which may comprise a grating receiving light, a first prism moveable to coarsely select an angle of incidence of the light on the grating, and a second prism moveable to finely select an angle of incidence of the light on the grating. In one application, the apparatus may be used as a line narrowing module for a laser light source. | 08-11-2011 |
Sergey Rylov, Yorktown Heights, NY US
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20140140439 | Power-Scalable Skew Compensation in Source-Synchronous Parallel Interfaces - A parallel receiver interface includes a plurality of parallel data receivers, each receiver receiving input data. A clock receiver is configured to receive a forwarded clock. A phase interpolator has an input coupled to the output of the clock receiver and has an output coupled to each of the parallel receivers. Parallel clock delay elements are within each of the parallel data receivers, each clock delay element configured to provide varying amounts of clock phase adjustment. Inputs of a multiplexer circuit within each of the parallel data receivers are coupled to the outputs of each of the parallel clock delay elements within a respective parallel data receiver. An output of the multiplexer circuit is coupled to a data sampler within the respective parallel data receiver, the multiplexer circuit being configured to be controlled by a logic signal. | 05-22-2014 |
Sergey V. Rylov, Yorktown Heights, NY US
Patent application number | Description | Published |
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20100328130 | TIME-TO-DIGITAL BASED ANALOG-TO-DIGITAL CONVERTER ARCHITECTURE - Apparatus and methods are provided relating to time-to-digital based analog-to-digital converter. An apparatus includes a time-to-digital converter based analog-to-digital converter for generating a first signal and a second signal having a timing relationship between a rising edge of the first signal and a rising edge of the second signal based on a sampled input analog voltage level, and converting the timing relationship into a corresponding time-to-digital representation. The time-to-digital representation is obtained without any voltage comparison and current comparison. | 12-30-2010 |
20100329403 | DYNAMIC QUADRATURE CLOCK CORRECTION FOR A PHASE ROTATOR SYSTEM - A system and method for closed loop clock correction includes adjusting two or more input signals comprising at least one in-phase clock and one quadrature clock, and applying adjusted quadrature clock signals to a device capable of generating a 4-quadrant interpolated output clock phase. An interpolated output clock phase is delayed to form a clock for a measurement device. Two or more adjusted input signals are measured on a measurement device over a range of interpolated output clock phases. Errors are determined on the in-phase clock and the quadrature clock using sampled information from the measurement device. The in-phase clock and the quadrature clock are adapted using determined error information. | 12-30-2010 |
Sergey V. Rylov, White Plains, NY US
Patent application number | Description | Published |
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20080225990 | APPARATUS AND METHOD FOR SIGNAL PHASE CONTROL IN AN INTEGRATED RADIO CIRCUIT - An apparatus and method to control signal phase in a radio device includes a phase rotator configured to control a phase of a local oscillator. A phase error determination module is configured to determine phase error information based on received in-phase (I) and quadrature (Q) (IQ) signal values. A phase correction module is configured to derive from the received IQ signal values a correction signal and apply the correction signal to the phase rotator in a path of the local oscillator. | 09-18-2008 |
20100054324 | SYSTEM AND METHOD FOR LATENCY REDUCTION IN SPECULATIVE DECISION FEEDBACK EQUALIZERS - A decision feedback equalizer (DFE) and method include summer circuits configured to add a dynamic feedback tap to a received input to provide a sum and to add a speculative static tap to the sum. Sense amplifiers are configured to receive outputs of the summer circuits and evaluate the outputs of the summer circuits in accordance with a clock signal. A passgate multiplexer is configured to receive outputs from sense amplifiers wherein the multiplexer is clock-gated for isolation of subsequent circuitry from the outputs of the sense amplifiers during a precharge period. A gating circuit is configured to perform gating of a select signal output from a second circuit portion with a clock signal and to enable the isolation of the subsequent circuitry by the multiplexer during the precharge period. A regenerative buffer is coupled to the multiplexer to maintain an output of the multiplexer during the precharge period, to provide the select signal for a passgate multiplexer in the second circuit portion of the DFE and to drive the dynamic feedback tap on the first circuit portion of the DFE. | 03-04-2010 |
20120313683 | PROGRAMMABLE DELAY GENERATOR AND CASCADED INTERPOLATOR - A programmable delay generator and a cascaded interpolator are provided. The programmable delay generator includes a first delay line and a second delay line, each having a respective plurality of stages of the same number. Each stage of the first line includes a respective delay buffer and has one signal input and one signal output. Each stage of the second line includes a respective selecting element and has two signal inputs, one select input for selecting one of the two signal inputs, and one signal output. The first line and the second line are configured in parallel, are interconnected, and have a same signal propagation direction. Each delay step provided by each stage of the second line is equal to a difference between a delay through one stage of the first line and a delay through one stage of the second line. | 12-13-2012 |
20120314721 | TIMING RECOVERY METHOD AND APPARATUS FOR AN INPUT/OUTPUT BUS WITH LINK REDUNDANCY - Methods and apparatus are provided for timing recovery for an input/output bus with link redundancy. A parallel input/output interface receiver includes a plurality of data receivers, each configured to respectively receive input data from a respective one of n+m channels, where n is an integer greater than one and m is an integer greater than or equal to one. The input data is non-calibration data for the n channels and is calibration data for the m channels. The interface receiver further includes a first phase adjustor configured to provide a first clock signal to the plurality of data receivers for sampling of only the non-calibration data at any given time, and a second phase adjustor configured to provide a second clock signal to the plurality of data receivers for sampling of only the calibration data at any given time. | 12-13-2012 |
20130207707 | HIGH-RESOLUTION PHASE INTERPOLATORS - A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator. | 08-15-2013 |
20130207708 | HIGH-RESOLUTION PHASE INTERPOLATORS - A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator. | 08-15-2013 |
20130214865 | CAPACITIVE LEVEL-SHIFTING CIRCUITS AND METHODS FOR ADDING DC OFFSETS TO OUTPUT OF CURRENT-INTEGRATING AMPLIFIER - Capacitive level-shifting circuits and methods are provided for adding DC offsets to the output of a current-integrating amplifier. For example, a current-integrating amplifier includes an input amplifier stage and an output offset circuit. The input amplifier stage includes an input node, a first output node, and a first switch connected between the first output node and a power supply node. The output offset circuit is connected to the first output node of the input amplifier stage and to a second output node of the current-integrating amplifier. The output offset circuit includes a first series capacitor coupled between the first output node of the input amplifier stage and the second output node of the current-integrating amplifier. The output offset circuit switchably connects a bias voltage to the second output node and charges the first series capacitor to add a DC offset to the second output node of the current-integrating amplifier. | 08-22-2013 |
20140176213 | PROGRAMMABLE DELAY GENERATOR AND CASCADED INTERPOLATOR - A programmable delay generator and a cascaded interpolator are provided. The cascaded interpolator includes a set of interpolator stages, each having two signal inputs and two signal outputs, configured to receive two input signals having two different phases and to generate two output signals that have a phase separation equal to a fraction of a phase separation of the two input signals; and a phase converter connected to a last stage of the plurality of single-bit interpolator stages, configured to convert the two output signals into a single final output signal of a given phase. | 06-26-2014 |
Sergey Vladimirovich Rylov, White Plains, NY US
Patent application number | Description | Published |
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20090195286 | PHASE SHIFTING USING ASYMMETRIC INTERPOLATOR WEIGHTS - Illustrative embodiments provide an apparatus for phase shifting to produce uniform phase steps in a predictable manner to improve the linearity of conversion. The apparatus comprises a phase selector for selecting two or more phases to create selected phases and a phase interpolator capable of receiving the selected phases. The apparatus further comprises a set of digital to analog converter cells connected to the phase interpolator, wherein interpolator weight distribution among the set of digital to analog converter cells is non-linear, and a thermometer code in communication with the set of digital to analog converter cells, wherein the thermometer code adjusts output of the set of digital to analog converter cells to phase shift the selected phases. | 08-06-2009 |
20100109734 | CURRENT-MODE PHASE ROTATOR WITH PARTIAL PHASE SWITCHING - In one illustrative embodiment, an apparatus for a current-mode phase rotator with partial input phase switching comprises a mixer, wherein the mixer is a four quadrant current-mode mixer comprised of four interpolation buffers, wherein each interpolation buffer receives as input a clock phase from a set of four equidistant clock phases, and a set of two-output current-steering digital to analog converters that supply tail currents to the mixer wherein a first digital to analog converter has additional switches to connect each of two outputs to one of two polarities of a given clock while each remaining digital to analog converter has no additional switches and has two outputs supplying current only to two different polarities of a same clock phase wherein steering the current during incremental rotation about a phase circle defines an octagonal shaped phase envelope. | 05-06-2010 |