Patent application number | Description | Published |
20120198312 | METHODS AND DEVICES TO INCREASE MEMORY DEVICE DATA RELIABILITY - A first data set is written to first memory units identified as having a higher data reliability and a second data set is written to second memory units identified as having a lower data reliability than the first memory units. In some cases, the second data set may include metadata or redundancy information that is useful to aid in reading and/or decoding the first data set. The act of writing the second data set increases the data reliability of the first data set. The second data set may be a null pattern, such as all erased bits. | 08-02-2012 |
20120278564 | SECURE ERASURE OF DATA FROM A NON-VOLATILE MEMORY - Method and apparatus for securely erasing data from a non-volatile memory, such as but not limited to a flash memory array. In accordance with various embodiments, an extended data set to be sanitized from the memory is identified. The extended data set includes multiple copies of data having a common logical address and different physical addresses within the memory. The extended data set is sanitized in relation to a characterization of the data set. The data sanitizing operation results in the extended data set being purged from the memory and other previously stored data in the memory being retained. | 11-01-2012 |
20120278579 | Self-Initiated Secure Erasure Responsive to an Unauthorized Power Down Event - Method and apparatus for self-initiated secure erasure of data from a non-volatile memory, such as a solid state drive (SSD). In accordance with various embodiments, the memory is operated in communication with a host device. A self-initiated, non-destructive secure erasure of the data stored in the memory is carried out responsive to a detection of an unauthorized power down event associated with the memory. | 11-01-2012 |
20120300554 | Sanitizing a Non-Volatile Memory Through Charge Accumulation - Method and apparatus for sanitizing a non-volatile memory, such as a flash memory array. In accordance with various embodiments, a memory cell is sanitized by using a write circuit to accumulate charge on a floating gate of the cell to a level such that application of a maximum available read sensing voltage to a control gate of the cell is insufficient to place the cell in a conductive state. | 11-29-2012 |
20130007380 | LIMITING ACTIVITY RATES THAT IMPACT LIFE OF A DATA STORAGE MEDIA - A first cumulative data transfer over a first time window from an intermediary module to a data storage media is determined. The intermediary module is coupled between a host interface and the data storage media. An activity rate from the intermediary module to the data storage media is limited for one or more subsequent time windows if the first cumulative activity rate exceeds a threshold value that impacts life of the data storage media. The limitation of the activity rate is removed after the one or more subsequent time windows expire | 01-03-2013 |
20130007543 | ESTIMATING TEMPORAL DEGRADATION OF NON-VOLATILE SOLID-STATE MEMORY - Representative locations of a non-volatile, solid-state memory of an apparatus store characterization data. An event during which elapsed time is not measured by the apparatus is determined. In response to the event, temporal degradation of the non-volatile, solid-state memory during the event is estimated based on electrical characteristics of the representative locations. | 01-03-2013 |
20130258770 | Parametric Tracking to Manage Read Disturbed Data - Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with various embodiments, data are stored in a first location in a memory, and read from the first location a selected number of times. At least one parameter associated with the first location is measured after the data are read the selected number of times. The data are thereafter migrated to a second location in the memory responsive to the measured parameter indicating a presence of read disturbance in the data in the first location. | 10-03-2013 |
20130322169 | MULTI-LEVEL CELL (MLC) UPDATE WITH PROTECTED MODE CAPABILITY - Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, a first block of data is written to a group of memory cells at a first memory location in single-level cell (SLC) mode. The first block of data is copied from the first memory location to a group of memory cells at a second memory location to provide a backup copy of the first block of data during a protected mode of operation. A second block of data is subsequently overwritten to the group of memory cells at the first memory location so that the first memory location stores both the first and second blocks of data in multi-level cell (MLC) mode. | 12-05-2013 |
20130326114 | WRITE MITIGATION THROUGH FAST REJECT PROCESSING - Apparatus and method for data management in a memory, such as but not limited to a flash memory array. In accordance with some embodiments, a first hash value associated with a first set of data stored in a memory is compared to a second hash value associated with a second set of data pending storage to the memory. The second set of data is stored in the memory responsive to a mismatch between the first and second hash values. | 12-05-2013 |
20130326115 | BACKGROUND DEDUPLICATION OF DATA SETS IN A MEMORY - Apparatus and method for data management in a memory, such as but not limited to a flash memory array. In accordance with some embodiments, a plurality of data sets in a memory are identified as having a common data content and different physical addresses in the memory. A selected one of the data sets is marked as valid data and the remaining data sets are marked as stale data responsive to evaluation of at least one variable parameter associated with the physical addresses at which the data sets are respectively stored. | 12-05-2013 |
20130326116 | ALLOCATING MEMORY USAGE BASED ON QUALITY METRICS - A tiered memory system includes a memory controller for a primary memory and a secondary memory, where the secondary memory is used as a cache for the primary memory. The memory controller is configured to cause redundant data that is stored in the primary memory of the memory system to be stored in first memory locations of the secondary memory. The controller causes data that is not stored in the primary memory to be stored in second memory locations of the secondary memory. The second memory locations have at least one of lower bit error rate and higher access speed than the first memory locations. | 12-05-2013 |
20140013047 | DEFINING ADDRESS RANGES USED TO CACHE SPECULATIVE READ DATA - A host read request affects a request address range of a main storage. A speculative address range proximate to the request address range is defined. Speculative data stored in the speculative address range is not requested via the host read request. A criterion is determined that is indicative of future read requests of associated with the speculative data. The speculative data is copied from the main storage to at least one of a non-volatile cache and a volatile cache together with data of the host read request in response to the criterion meeting a threshold. The non-volatile cache and the volatile cache mirror respective portions of the main storage. | 01-09-2014 |
20140013052 | CRITERIA FOR SELECTION OF DATA FOR A SECONDARY CACHE - Host read operations affecting a first logical block address of a data storage device are tracked. The data storage device includes a main storage and a non-volatile cache that mirrors a portion of data of the main storage. One or more criteria associated with the host read operations are determined. The criteria are indicative of future read requests of second logical block address associated with the first logical block address. Data of the at least the second logical block address is copied from the main storage to the non-volatile cache if the criteria meets a threshold. | 01-09-2014 |
20140013053 | DETERMINING A CRITERION FOR MOVEMENT OF DATA FROM A PRIMARY CACHE TO A SECONDARY CACHE - A new segment of data is copied to a volatile, primary cache based on a host data read access request. The primary cache mirrors a first portion of a non-volatile main storage criterion is determined for movement of data from the primary cache to a non-volatile, secondary cache that mirrors a second portion of the main storage. The criterion gives higher priority to segments having addresses not yet selected for reading by the host. In response to the new segment of data being copied to the primary cache, a selected segment of data is copied from the primary cache to the secondary cache in response to the selected segment satisfying the criterion. | 01-09-2014 |
20140052897 | DYNAMIC FORMATION OF GARBAGE COLLECTION UNITS IN A MEMORY - Method and apparatus for managing data in a memory, such as but not limited to a flash memory. In accordance with some embodiments, a memory is provided with a plurality of addressable data storage blocks which are arranged into a first set of garbage collection units (GCUs). The blocks are rearranged into a different, second set of GCUs responsive to parametric performance of the blocks. | 02-20-2014 |
20140115232 | Metadata Journaling with Error Correction Redundancy - Method and apparatus for managing a memory, such as but not limited to a flash memory. In accordance with some embodiments, user data and associated metadata are stored in a memory. The metadata are arranged as a first sequence of snapshots of the metadata at different points in time during the operation of the memory, and a second sequence of intervening journals which reflect updates to the metadata from one snapshot to the next. Requested portions of the metadata are recovered from the memory using a selected snapshot in the first sequence and first and second journals in the second sequence. | 04-24-2014 |
20140115233 | Restoring Virtualized GCU State Information - Method and apparatus for managing a memory, such as but not limited to a flash memory. In accordance with some embodiments, initial state information is stored which identifies an actual state of a garbage collection unit (GCU) of a memory during a normal operational mode. During a restoration mode after a memory power cycle event, a virtualized state of the GCU is determined responsive to the initial state information and to data read from the GCU. The memory is transitioned from the restoration mode to the normal operational mode once the virtualized state for the GCU is determined. | 04-24-2014 |
20140129891 | METHODS AND DEVICES TO INCREASE MEMORY DEVICE DATA RELIABILITY - A first data set is written to first memory units identified as having a higher data reliability and a second data set is written to second memory units identified as having a lower data reliability than the first memory units. In some cases, the second data set may include metadata or redundancy information that is useful to aid in reading and/or decoding the first data set. The act of writing the second data set increases the data reliability of the first data set. The second data set may be a null pattern, such as all erased bits. | 05-08-2014 |
20140219001 | APPLYING A BIAS SIGNAL TO MEMORY CELLS TO REVERSE A RESISTANCE SHIFT OF THE MEMORY CELLS - Data is written to cells of a resistance-based, non-volatile memory. An activity metric is tracked since the writing of the data to the cells. In response to the activity metric satisfying a threshold, a bias signal is applied to the cells to reverse a resistance shift of the cells. | 08-07-2014 |
20140219034 | Non-Volatile Write Buffer Data Retention Pending Scheduled Verification - Method and apparatus for managing data in a memory. In accordance with some embodiments, a non-volatile (NV) buffer is adapted to store input write data having a selected logical address. A write circuit is adapted to transfer a copy of the input write data to an NV main memory while retaining the stored input write data in the NV buffer. A verify circuit is adapted to perform a verify operation at the conclusion of a predetermined elapsed time interval to verify successful transfer of the copy of the input write data to the NV main memory. The input write data are retained in the NV buffer until successful transfer is verified. | 08-07-2014 |
20140241032 | METHODS AND APPARATUSES USING A TRANSFER FUNCTION TO PREDICT RESISTANCE SHIFTS AND/OR NOISE OF RESISTANCE-BASED MEMORY - Two or more workload indicators affecting a memory cell of a resistance-based, non-volatile memory are measured. The two or more workload indicators are applied to a transfer function that predicts a resistance shift and/or resistance noise variance in response to the two or more workload indicators. A result of the transfer function is applied to shift and/or determine a threshold resistance used for at least one of a program operation and a read operation affecting the memory cell. An error rate of the memory cell is reduced as a result. | 08-28-2014 |
20140241033 | Management of Variable Resistance Data Storage Device - Various embodiments may generally be directed to a variable resistance data storage device and a method of managing the device. A data storage device may have at least a controller configured to re-characterize at least one variable resistance memory cell in response to an identified variance from a predetermined resistance threshold. | 08-28-2014 |
20140241071 | Fast Power Loss Recovery By Swapping Boot and Recovery Data Sets in a Memory - Method and apparatus for managing data in a memory. In accordance with some embodiments, a recovery data set representing a current state of a storage device is stored in a rewritable non-volatile memory responsive to detection of a potentially imminent deactivation of the device. The recovery data set is swapped with a boot data set in said memory responsive to subsequent deactivation of the device. The boot data set is subsequently used to transition the device from a deactivated mode to an operationally ready mode during device reinitialization. The boot data set is thereafter swapped with the recovery data set to return the device to the current state. | 08-28-2014 |
20140244892 | ASSIGNING A WEIGHTING TO HOST QUALITY OF SERVICE INDICATORS - Quality of service indicators are provided from a host via a host interface. The quality of service indicators relate to data stored in a non-volatile data storage via the host. Workload indicators related to the quality of service indicators are measured, and a weighting is assigned to the host in response to a correlation between the quality of service indicators and the measured workload indicators. The weighting is applied to the quality of service indicators when responding to data access requests from the host. | 08-28-2014 |
20140244896 | Data Update Management in a Cloud Computing Environment - Method and apparatus for managing data in a cloud computing environment. In accordance with some embodiments, data updates are received to a multi-tier memory structure across a cloud network and stored as working data in an upper rewritable non-volatile memory tier of the memory structure. The working data are periodically logged to a lower non-volatile memory tier in the memory structure while a current version of the working data remain in the upper memory tier. The upper and lower memory tiers each are formed of rewritable memory cells having different constructions and storage attributes. | 08-28-2014 |
20140244897 | Metadata Update Management In a Multi-Tiered Memory - Method and apparatus for managing data in a memory. In accordance with some embodiments, metadata updates are stored in a first tier of a a multi-tier non-volatile memory structure responsive to access operations associated with data objects in the memory structure. The stored metadata updates are logged in a second, lower tier of the memory structure. The stored metadata updates are further migrated to a different location within the first tier responsive to an accumulated count of said access operations. | 08-28-2014 |
20140245108 | ECC Management for Variable Resistance Memory Cells - A data storage device may generally be constructed and operated with at least a controller configured to identify a variance from a predetermined threshold in at least one variable resistance memory cell and upgrade a first error correction code (ECC) level to a second ECC level for the at least one variable resistance memory cell. | 08-28-2014 |
20140258646 | FORMING A CHARACTERIZATION PARAMETER OF A RESISTIVE MEMORY ELEMENT - An incremental signal is defined that includes at least one of a duration and a peak voltage that is less than a respective minimum programming time or minimum programming voltage step of a resistive memory element. A characterization procedure is repeatedly performed that at least involves: applying a signal to the memory element, the signal being incremented by the incremental signal during each subsequent application; measuring a first resistance of the memory element in response to the signal; and c) measuring a second resistance of the memory element after a time period has elapsed from the measurement of the first resistance with no programming signal applied. In response to the first and second resistance measurements of the characterization procedure, a characterization parameter of the memory element is formed. | 09-11-2014 |
20140281280 | SELECTING BETWEEN NON-VOLATILE MEMORY UNITS HAVING DIFFERENT MINIMUM ADDRESSABLE DATA UNIT SIZES - An apparatus includes a controller capable of being coupled to a host interface and a memory device. The memory device includes two or more non-hierarchical, non-volatile memory units having different minimum addressable data unit sizes. The controller is configured to at least perform determining a workload indicator of a data object being stored in the memory device via the host interface. The controller selects one of the memory units in response to the workload indicator of the data object corresponding to the minimum addressable data unit size of the selected memory unit corresponding to the workload indicator. The data object is stored in the selected memory unit in response thereto. | 09-18-2014 |
20150074486 | TRANSFER UNIT MANAGEMENT - Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a non-volatile memory is arranged into a plurality of blocks, with each of the blocks constituting an integral plural number N of fixed-sized, multi-bit transfer units. A processing circuit retrieves at least a portion of the data stored in a selected block to a volatile memory buffer in response to a transfer unit (TU) bit map. The TU bit map is stored in a memory and provides a multi-bit sequence of bits corresponding to the N transfer units of the selected block. The values of the bits in the multi-bit sequence of bits indicate whether the corresponding transfer units are to be retrieved. | 03-12-2015 |
20150074487 | Memory Device with Variable Code Rate - Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, the apparatus has a solid-state non-volatile memory and a processing circuit configured to write data to a selected location of the memory. The data are arranged in the form of multi-bit code words each comprising a user data payload and associated parity data configured to correct one or more bit errors in the user data payload. The processing circuit adjusts at least a selected one of a size of the code words, a size of the user data payloads or a size of the parity data responsive to at least a selected one of an accumulated count of access operations upon the selected location or an error rate associated with the selected location. | 03-12-2015 |
20150089119 | COMMAND EXECUTION USING EXISTING ADDRESS INFORMATION - Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory module has a plurality of solid-state non-volatile memory cells. A controller communicates a first command having address information and a first operation code. The first operation code identifies a first action to be taken by the memory module in relation to the address information. The controller subsequently communicates a second command having a second operation code without corresponding address information. The memory module takes a second action identified by the second command using the address information from the first command. | 03-26-2015 |
20150089278 | VARIABLE DATA RECOVERY SCHEME HIERARCHY - Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory has a plurality of solid-state non-volatile memory cells. A processing circuit is connected to the memory and configured to direct the execution of a plurality of read error recovery routines in response to at least one uncorrectable read error in a data set retrieved from the memory. The recovery routines are executed in a selected order based on an elapsed recovery time parameter for each of the recovery routines and an estimated probability of success of each of the recovery routines. | 03-26-2015 |