Patent application number | Description | Published |
20130040450 | Methods of Forming a Dielectric Cap Layer on a Metal Gate Structure - Disclosed herein are various methods of forming metal-containing insulating material regions on a metal layer of a gate structure of a semiconductor device. In one example, the method includes forming a gate structure of a transistor, the gate structure comprising at least a first metal layer, and forming a first metal-containing insulating material region in the first metal layer by performing a gas cluster ion beam process using to implant gas molecules into the first metal layer. | 02-14-2013 |
20130078791 | SEMICONDUCTOR DEVICE FABRICATION METHODS WITH ENHANCED CONTROL IN RECESSING PROCESSES - Semiconductor device fabrication methods having enhanced control in recessing processes are provided. In a method for fabricating a semiconductor device or plurality of them, a structure is formed. The method includes preparing a limited amount of the structure having a depth of less than ten atomic layers for removal. Further, the method includes performing a removal process to remove the limited amount of the structure. The method repeats preparation of successive limited amounts of the structure for removal, and performance of the removal process to form a recess at an upper portion of the structure. | 03-28-2013 |
20130161729 | Methods of Forming Isolation Structures on FinFET Semiconductor Devices - One illustrative method disclosed herein includes performing at least one etching process on a semiconducting substrate to form a plurality of trenches and a plurality of fins for the FinFET device in the substrate, forming a first layer of insulating material in the trenches, wherein an upper surface of the first layer of insulating material is below an upper surface of the substrate, forming an isolation layer within the trenches above the first layer of insulating material, wherein the isolation layer has an upper surface that is below the upper surface of the substrate, forming a second layer of insulating material above the isolation layer, wherein the second layer of insulating material has an upper surface that is below the upper surface of the substrate, and forming a gate electrode structure above the second layer of insulating material. | 06-27-2013 |
20130181263 | Methods of Forming a Dielectric Cap Layer on a Metal Gate Structure - Disclosed herein are various methods of forming isolation structures on FinFETs and other semiconductor devices, and the resulting devices that have such isolation structures. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define a fin for a FinFET device, forming a layer of insulating material in the trenches, wherein the layer of insulating material covers a lower portion of the fin but not an upper portion of the fin, forming a protective material on the upper portion of the fin, and performing a heating process in an oxidizing ambient to form a thermal oxide region on the covered lower portion of the fin. | 07-18-2013 |
20130187203 | FORMATION OF THE DIELECTRIC CAP LAYER FOR A REPLACEMENT GATE STRUCTURE - Gate to contact shorts are reduced by forming dielectric caps in replaced gate structures. Embodiments include forming a replaced gate structure on a substrate, the replaced gate structure including an ILD having a cavity, a first metal on a top surface of the ILD and lining the cavity, and a second metal on the first metal and filling the cavity, planarizing the first and second metals, forming an oxide on the second metal, removing the oxide, recessing the first and second metals in the cavity, forming a recess, and filling the recess with a dielectric material. Embodiments further include dielectric caps having vertical sidewalls, a trapezoidal shape, a T-shape, or a Y-shape. | 07-25-2013 |
20130187228 | FinFET Semiconductor Devices with Improved Source/Drain Resistance and Methods of Making Same - Disclosed herein are various FinFET semiconductor devices with improved source/drain resistance and various methods of making such devices. One illustrative device disclosed herein includes a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches at least partially define a fin for the device, an etch stop layer positioned above a bottom surface of each of the trenches, and a metal silicide region formed on all exposed surfaces of the fin that are positioned above an upper surface of the etch stop layer. | 07-25-2013 |
20130187236 | Methods of Forming Replacement Gate Structures for Semiconductor Devices - Disclosed herein are methods of forming replacement gate structures. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, removing the sacrificial gate structure to thereby define a gate cavity, forming a layer of insulating material in the gate cavity and forming a layer of metal within the gate cavity above the layer of insulating material. The method further includes forming a sacrificial material in the gate cavity so as to cover a portion of the layer of metal and thereby define an exposed portion of the layer of metal, performing an etching process on the exposed portion of the layer of metal to thereby remove the exposed portion of the layer of metal from within the gate cavity, and, after performing the etching process, removing the sacrificial material and forming a conductive material above the remaining portion of the layer of metal. | 07-25-2013 |
20130292805 | METHODS OF FORMING SPACERS ON FINFETS AND OTHER SEMICONDUCTOR DEVICES - Disclosed herein are various methods of forming spacers on FinFETs and other semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate that defines a fin, forming a first layer of insulating material in the trenches that covers a lower portion of the fin but exposes an upper portion of the fin, and forming a second layer of insulating material on the exposed upper portion of the fin. The method further comprises selectively forming a dielectric material above an upper surface of the fin and in a bottom of the trench, depositing a layer of spacer material above a gate structure of the device and above the dielectric material above the fin and in the trench, and performing an etching process on the layer of spacer material to define sidewall spacers positioned adjacent the gate structure. | 11-07-2013 |
20130307032 | METHODS OF FORMING CONDUCTIVE CONTACTS FOR A SEMICONDUCTOR DEVICE - One illustrative method disclosed herein involves forming a contact opening in a layer of insulating material, forming a layer of conductive material above the layer of insulating material that overfills the contact opening, performing at least one chemical mechanical polishing process to remove portions of the conductive material positioned outside of the contact opening and thereby define a conductive contact positioned in the contact opening and, after performing the chemical mechanical polishing process, performing a selective metal deposition process to selectively form additional metal material on an upper surface of the conductive contact. | 11-21-2013 |
20130307087 | METHOD FOR FORMING A SELF-ALIGNED CONTACT OPENING BY A LATERAL ETCH - A self-aligned source/drain contact formation process without spacer or cap loss is described. Embodiments include providing two gate stacks, each having spacers on opposite sides, and an interlayer dielectric (ILD) over the two gate stacks and in a space therebetween, forming a vertical contact opening within the ILD between the two gate stacks, and laterally removing ILD between the two gate stacks from the vertical contact opening toward the spacers, to form a contact hole. | 11-21-2013 |
20130309868 | METHODS FOR FORMING AN INTEGRATED CIRCUIT WITH STRAIGHTENED RECESS PROFILE - Methods are provided for forming an integrated circuit. In an embodiment, the method includes forming a sacrificial mandrel overlying a base substrate. Sidewall spacers are formed adjacent sidewalls of the sacrificial mandrel. The sidewall spacers have a lower portion that is proximal to the base substrate, and the lower portion has a substantially perpendicular outer surface relative to the base substrate. The sidewall spacers also have an upper portion that is spaced from the base substrate. The upper portion has a sloped outer surface. A first dielectric layer is formed overlying the base substrate and is conformal to at least a portion of the upper portion of the sidewall spacers. The upper portion of the sidewall spacers is removed after forming the first dielectric layer to form a recess having a re-entrant profile in the first dielectric layer. The re-entrant profile of the recess is straightened. | 11-21-2013 |
20130328111 | RECESSING AND CAPPING OF GATE STRUCTURES WITH VARYING METAL COMPOSITIONS - A method for recessing and capping metal gate structures is disclosed. Embodiments include: forming a dummy gate electrode on a substrate; forming a hard mask over the dummy gate electrode; forming spacers on opposite sides of the dummy gate electrode and the hard mask; forming an interlayer dielectric (ILD) over the substrate adjacent the spacers; forming a first trench in the ILD down to the dummy gate electrode; removing the dummy gate electrode to form a second trench below the first trench; forming a metal gate structure in the first and second trenches; and forming a gate cap over the metal gate structure. | 12-12-2013 |
20130328112 | SEMICONDUCTOR DEVICES HAVING IMPROVED GATE HEIGHT UNIFORMITY AND METHODS FOR FABRICATING SAME - Semiconductor devices and methods for fabricating semiconductor devices are provided. In an embodiment, a method for fabricating a semiconductor device includes forming on a semiconductor surface a temporary gate structure including a polysilicon gate and a cap. A spacer is formed around the temporary gate structure. The cap and a portion of the spacer are removed. A uniform liner is deposited overlying the polysilicon gate. The method removes a portion of the uniform liner overlying the polysilicon gate and the polysilicon gate to form a gate trench. Then, a replacement metal gate is formed in the gate trench. | 12-12-2013 |
20140035010 | INTEGRATED CIRCUIT HAVING A REPLACEMENT GATE STRUCTURE AND METHOD FOR FABRICATING THE SAME - A method for fabricating an integrated circuit includes forming a temporary gate structure on a semiconductor substrate. The temporary gate structure includes a temporary gate material disposed between two spacer structures. The method further includes forming a first directional silicon nitride liner overlying the temporary gate structure and the semiconductor substrate, etching the first directional silicon nitride liner overlying the temporary gate structure and the temporary gate material to form a trench between the spacer structures, while leaving the directional silicon nitride liner overlying the semiconductor substrate in place, and forming a replacement metal gate structure in the trench. An integrated circuit includes a replacement metal gate structure overlying a semiconductor substrate, a silicide region overlying the semiconductor substrate and positioned adjacent the replacement gate structure; a directional silicon nitride liner overlying a portion of the replacement gate structure; and a contact plug in electrical communication with the silicide region. | 02-06-2014 |
20140042502 | SEMICONDUCTOR DEVICES WITH SELF-ALIGNED CONTACTS AND LOW-K SPACERS - One illustrative method disclosed herein includes removing a portion of a sacrificial sidewall spacer to thereby expose at least a portion of the sidewalls of a sacrificial gate electrode and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode. In this example, the method also includes forming a sacrificial gap fill material above the liner layer, exposing and removing the sacrificial gate electrode to thereby define a gate cavity that is laterally defined by the liner layer, forming a replacement gate structure, removing the sacrificial gap fill material and forming a low-k sidewall spacer adjacent the liner layer. A device is also disclosed that includes a gate cap layer, a layer of silicon nitride or silicon oxynitride positioned on each of two upstanding portions of a gate insulation layer and a low-k sidewall spacer positioned on the layer of silicon nitride or silicon oxynitride. | 02-13-2014 |
20140054723 | ISOLATION STRUCTURES FOR FINFET SEMICONDUCTOR DEVICES - One illustrative device disclosed herein includes a plurality of fins separated by a trench formed in a semiconducting substrate, a first layer of insulating material positioned in the trench, the first layer of insulating material having an upper surface that is below an upper surface of the substrate, an isolation layer positioned within the trench above the first layer of insulating material, the isolation layer having an upper surface that is below the upper surface of the substrate, a second layer of insulating material positioned within the trench above the isolation layer, the second layer of insulating material having an upper surface that is below the upper surface of the substrate, and a gate structure positioned above the second layer of insulating material. | 02-27-2014 |
20140077274 | INTEGRATED CIRCUITS WITH IMPROVED GATE UNIFORMITY AND METHODS FOR FABRICATING SAME - Integrated circuits with improved gate uniformity and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure including a first region and a second region and a structure surface formed by the first region and the second region. The first region is formed by a first material and the second region is formed by a second material. In the method, the structure surface is exposed to a gas cluster ion beam (GCIB) and an irradiated layer is formed in the structure in both the first region and the second region. The irradiated layer is etched to form a recess. | 03-20-2014 |
20140110798 | METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH LOW-K SPACERS AND THE RESULTING DEVICE - One method disclosed herein includes forming at least one sacrificial sidewall spacer adjacent a sacrificial gate structure that is formed above a semiconducting substrate, removing at least a portion of the sacrificial gate structure to thereby define a gate cavity that is laterally defined by the sacrificial spacer, forming a replacement gate structure in the gate cavity, removing the sacrificial spacer to thereby define a spacer cavity adjacent the replacement gate structure, and forming a low-k spacer in the spacer cavity. A novel device disclosed herein includes a gate structure positioned above a semiconducting substrate, wherein the gate insulation layer has two upstanding portions that are substantially vertically oriented relative to an upper surface of the substrate. The device further includes a low-k sidewall spacer positioned adjacent each of the vertically oriented upstanding portions of the gate insulation layer. | 04-24-2014 |
20140138779 | INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH REDUCED PARASITIC CAPACITANCE - Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a sacrificial gate structure over a semiconductor substrate. A spacer is formed around the sacrificial gate structure and a dielectric material is deposited over the spacer and semiconductor substrate. The method includes selectively etching the spacer to form a trench between the sacrificial gate structure and the dielectric material. The trench is bounded by a trench surface upon which a replacement spacer material is deposited. The method merges an upper region of the replacement spacer material to enclose a void within the replacement spacer material. | 05-22-2014 |
20140145257 | SEMICONDUCTOR DEVICE HAVING A METAL RECESS - Provided is a semiconductor device (e.g., transistor such as a FinFET or planar device) having a a liner layer and a metal layer (e.g., Tungsten (W)) in a trench (e.g., via CVD and/or ALD). A single chamber (e.g., an extreme fill chamber) will be utilized to separately etch back the liner layer and the metal layer. In general, the liner layer may be etched back further than the metal layer to provide for larger contact and lower resistance. After etching is complete, a bottom-up fill/growth of metal (e.g., W) will be performed (e.g., via CVD in a W chamber or the like) to increase the presence of gate metal in the trench. | 05-29-2014 |
20140159169 | RECESSING AND CAPPING OF GATE STRUCTURES WITH VARYING METAL COMPOSITIONS - A approach for recessing and capping metal gate structures is disclosed. Embodiments include: forming a dummy gate electrode on a substrate; forming a hard mask over the dummy gate electrode; forming spacers on opposite sides of the dummy gate electrode and the hard mask; forming an interlayer dielectric (ILD) over the substrate adjacent the spacers; forming a first trench in the ILD down to the dummy gate electrode; removing the dummy gate electrode to form a second trench below the first trench; forming a metal gate structure in the first and second trenches; and forming a gate cap over the metal gate structure. | 06-12-2014 |
20140203376 | FINFET INTEGRATED CIRCUITS WITH UNIFORM FIN HEIGHT AND METHODS FOR FABRICATING THE SAME - Methods for fabricating FinFET integrated circuits with uniform fin height and ICs fabricated from such methods are provided. A method includes etching a substrate using an etch mask to form fins. A first oxide is formed between the fins. A first etch stop is deposited on the first oxide. A second oxide is formed on the first etch stop. A second etch stop is deposited on the second oxide. A third oxide is deposited overlying the second etch stop. An STI extends from at least a surface of the substrate to at least a surface of the second etch stop overlying the fins to form a first active region and a second active region. The first etch stop overlying the fins is removed. The third oxide is removed to expose the second etch stop. A gate stack is formed overlying a portion of each of the fins. | 07-24-2014 |
20140299924 | FORMATION OF THE DIELECTRIC CAP LAYER FOR A REPLACEMENT GATE STRUCTURE - Gate to contact shorts are reduced by forming dielectric caps in replaced gate structures. Embodiments include forming a replaced gate structure on a substrate, the replaced gate structure including an ILD having a cavity, a first metal on a top surface of the ILD and lining the cavity, and a second metal on the first metal and filling the cavity, planarizing the first and second metals, forming an oxide on the second metal, removing the oxide, recessing the first and second metals in the cavity, forming a recess, and filling the recess with a dielectric material. Embodiments further include dielectric caps having vertical sidewalls, a trapezoidal shape, a T-shape, or a Y-shape. | 10-09-2014 |
20150044855 | METHODS OF FORMING SPACERS ON FINFETS AND OTHER SEMICONDUCTOR DEVICES - Disclosed herein are various methods of forming spacers on FinFETs and other semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate that defines a fin, forming a first layer of insulating material in the trenches that covers a lower portion of the fin but exposes an upper portion of the fin, and forming a second layer of insulating material on the exposed upper portion of the fin. The method further comprises selectively forming a dielectric material above an upper surface of the fin and in a bottom of the trench, depositing a layer of spacer material above a gate structure of the device and above the dielectric material above the fin and in the trench, and performing an etching process on the layer of spacer material to define sidewall spacers positioned adjacent the gate structure. | 02-12-2015 |
20150056796 | METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING A METAL GATE RECESS - Provided are approaches of forming a semiconductor device (e.g., transistor such as a FinFET or planar device) having a gate metal recess. In one approach, a liner layer and a metal layer (e.g., W) are applied in a trench (e.g., via CVD and/or ALD). Then, a single chamber (e.g., an extreme fill chamber) will be utilized to separately etch back the liner layer and the metal layer. In general, the liner layer may be etched back further than the metal layer to provide for larger contact and lower resistance. After etching is complete, a bottom-up fill/growth of metal (e.g., W) will be performed (e.g., via CVD in a W chamber or the like) to increase the presence of gate metal in the trench. | 02-26-2015 |