Rosa A.
Rosa A. Lukaszew, Williamsburg, VA US
Patent application number | Description | Published |
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20100164489 | System for Detecting Nanoparticles Using Modulated Surface Plasmon Resonance - A method and system for detecting magnetic nanoparticles include measuring a magneto-optical enhancement of the plasmon absorption in the optical response. | 07-01-2010 |
20120267552 | OPTICAL METHOD AND SYSTEM FOR MODIFYING MATERIAL CHARACTERISTICS USING SURFACE PLASMON POLARITON PROPAGATION - A method and system modify a material's characteristics. A first material has at least one characteristic that changes in the presence of electromagnetic energy, and a second material is positioned such that it is in contact with the first material. The second material is electrically conductive and sustains Surface Plasmon Polariton (SPP) excitation and propagation when electromagnetic radiation is coupled thereto. A diffraction grating is disposed at a planar region defined by one of the second material and a composite of the first material and second material. A beam of electromagnetic radiation is directed towards the diffraction grating at an acute angle with respect to the planar region. The electromagnetic radiation incident on the diffraction grating is coupled to the second material whereby SPP propagation generates an electromagnetic wave incident on at least a portion of the first material to thereby change its characteristics. | 10-25-2012 |
Rosa A. Orozco-Teran, Plano, TX US
Patent application number | Description | Published |
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20090215203 | MONITORING OF TEMPERATURE VARIATION ACROSS WAFERS DURING PROCESSING - A method of measuring temperature across wafers during semiconductor processing includes the step of providing a correlation between a peak wafer temperature during a processing step and a change in wafer surface charge or surface potential following the processing step. A first wafer to be characterized for its peak temperature spatial distribution during the processing step is processed through the processing step. The wafer surface charge or surface potential at a plurality of locations on the first wafer are measured following the processing step. A peak temperature spatial distribution for the first wafer is then determined based on the correlation and the wafer surface charge or surface potential measured in the measuring step. | 08-27-2009 |
Rosa A. Orozco-Teran, Richardson, TX US
Patent application number | Description | Published |
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20090017563 | PLASMA TREATMENT AND REPAIR PROCESSES FOR REDUCING SIDEWALL DAMAGE IN LOW-K DIELECTRICS - A method of forming an interconnect structure for an integrated circuit, including the steps of providing a substrate and forming a dielectric stack on the substrate including an etch-stop layer, a low-k dielectric layer, and a hardmask layer. The method further includes the steps of patterning a photoresist masking layer on the dielectric stack to define a plurality of feature defining regions and plasma processing the substrate in a plasma-based reactor, The processing step includes etching a plurality of features into the hardmask layer and at least a portion of the low-k dielectric layer and performing a plasma treatment process in situ in the plasma-based reactor, where the plasma treatment process includes flowing at least one hydrocarbon into the reactor and generating a plasma, where a mass flow rate of the hydrocarbon is at least 0.1 sccm. The method also includes forming a metal conductor in the plurality of features. | 01-15-2009 |
Rosa A. Orozco-Teran, Wappingers Falls, NY US
Patent application number | Description | Published |
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20150200137 | SELF-ALIGNED CONTACT STRUCTURE - Embodiments of present invention provide a method of forming a semiconductor structure. The method includes forming a semiconductor structure having a first metal layer and a plurality of dielectric layers on top of the first metal layer; creating one or more openings through the plurality of dielectric layers to expose the first metal layer underneath the plurality of dielectric layers; causing the one or more openings to expand downward into the first metal layer and expand horizontally into areas underneath the plurality of dielectric layers; applying a layer of lining material in lining sidewalls of the one or more openings inside the plurality of dielectric layers; and filling the expanded one or more openings with a conductive material. | 07-16-2015 |