Patent application number | Description | Published |
20080251779 | APPARATUS OF MEMORY ARRAY USING FINFETS - A memory cell includes a FinFET select device and a memory element. In some embodiments a memory cell has a contact element coupled between a surface of the fin and the memory element. | 10-16-2008 |
20080296703 | Method for Producing a Field-Effect Transistor, Field-Effect Transistor and Integrated Circuit Arrangement - A method for producing a tunnel field-effect transistor is disclosed. Connection regions of different doping types are produced by means of self-aligning implantation methods. | 12-04-2008 |
20090101975 | Integrated Circuit Arrangement Comprising a Field Effect Transistor, Especially a Tunnel Field Effect Transistor - An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric (GD | 04-23-2009 |
20090294832 | Semiconductor Device - One or more embodiments relate to a memory device, comprising: a substrate; a charge storage layer disposed over the substrate; and a control gate disposed over the charge storage layer, wherein the charge storage layer or the control gate layer comprises a carbon allotrope. | 12-03-2009 |
20100252799 | APPARATUS OF MEMORY ARRAY USING FINFETS - A memory cell includes a FinFET select device and a memory element. In some embodiments a memory cell has a contact element coupled between a surface of the fin and the memory element. | 10-07-2010 |
20100252895 | APPARATUS OF MEMORY ARRAY USING FINFETS - A memory cell includes a FinFET select device and a memory element. In some embodiments a memory cell has a contact element coupled between a surface of the fin and the memory element. | 10-07-2010 |
20110053331 | BIPOLAR TRANSISTOR FINFET TECHNOLOGY - This document discusses, among other things, apparatus having at least one CMOS transistor overlying a substrate; and at least one finned bipolar transistor overlying the substrate and methods for making the apparatus. | 03-03-2011 |
20110207282 | Methods for Producing a Tunnel Field-Effect Transistor - A method for producing a tunnel field-effect transistor is disclosed. Connection regions of different doping types are produced by means of self-aligning implantation methods. | 08-25-2011 |
20110233642 | SEMICONDUCTOR DEVICE - One or more embodiments relate to a memory device, comprising: a substrate; a gate stack disposed over the substrate, the gate stack comprising a control gate disposed over a charge storage layer; and a spacer select gate disposed over the substrate and laterally disposed from the gate stack, the select gate comprising a carbon allotrope. | 09-29-2011 |
20140024193 | Methods for Producing a Tunnel Field-Effect Transistor - A method for producing a tunnel field-effect transistor is disclosed. Connection regions of different doping types are produced by means of self-aligning implantation methods. | 01-23-2014 |
20140077146 | SEMICONDUCTOR DEVICE INCLUDING FINFET DEVICE - A memory element includes a FinFET select device and a memory element. In some embodiments a memory cell has a contact element coupled between a surface of the fin and the memory element. | 03-20-2014 |
Patent application number | Description | Published |
20080246016 | Device With Damaged Breakdown Layer - A device utilizing a breakdown layer in combination with a programmable resistance material, a phase-change material or a threshold switching material. The breakdown layer having damage. | 10-09-2008 |
20090072292 | SEMICONDUCTOR DEVICE AND METHOD OF MAKING SEMICONDUCTOR DEVICE - One or more embodiments are related to a semiconductor device, comprising: a high-K dielectric material; and a nitrogen-doped silicon material disposed over said high-k dielectric material. | 03-19-2009 |
20100182147 | REMOTE STORAGE OF DATA IN PHASE-CHANGE MEMORY - A security circuit comprising including a sensor located remotely from a central alarm handler and configured to sense an attack, and a phase-change memory cell coupled to and located remotely with the sensor, and configured to store an alarm event when the attack is sensed. | 07-22-2010 |
20100203703 | Deep Trench Isolation Structures and Methods of Formation Thereof - Deep trench isolation structures and methods of formation thereof are disclosed. Several methods of and structures for increasing the threshold voltage of a parasitic transistor formed proximate deep trench isolation structures are described, including implanting a channel stop region into the bottom surface of the deep trench isolation structures, partially filling a bottom portion of the deep trench isolation structures with an insulating material, and/or filling at least a portion of the deep trench isolation structures with a doped polysilicon material. | 08-12-2010 |
20100301896 | PHASE-CHANGE MEMORY SECURITY DEVICE - A semiconductor chip having a subcircuit formed in a substrate; and a phase-change memory cell located on the subcircuit, and configured to directly detect an attack on the subcircuit, or to form a shield to prevent physical access to the subcircuit. | 12-02-2010 |
20110171803 | INTEGRATED MEMORY DEVICE HAVING COLUMNS HAVING MULTIPLE BIT LINES - A memory device using tunneling field effect transistors (TFET) and buried bit lines is presented. The memory device includes a matrix containing rows and columns of storage cells. Each storage cell contains at least one cell transistor, which in turn contains first doped regions and second doped regions, one of which is a source and the other a drain. The memory device includes word lines, each of which is connected to storage cells of one row and bit lines, each of which is connected to storage cells of one column. The first doped regions are of a different doping type than the second doped regions. | 07-14-2011 |
20120068149 | APPARATUS OF MEMORY ARRAY USING FINFETS - In one or more embodiments, a semiconductor device a FinFET device and a second device. In one or more embodiments, the semiconductor device has a contact element coupled between a surface of the fin and the second device. | 03-22-2012 |
20140124827 | Integrated Circuit Arrangement Comprising a Field Effect Transistor, Especially a Tunnel Field Effect Transistor - Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor. An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric in comparison with other transistors on the same integrated circuit arrangement. As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions of the tunnel field effect transistor. | 05-08-2014 |