Patent application number | Description | Published |
20080307146 | STRUCTURE FOR DYNAMICALLY SCALABLE QUEUES FOR PERFORMANCE DRIVEN PCI EXPRESS MEMORY TRAFFIC - A method, computer system, and PCI Express device/protocol for a design structure that enables high performance IO data transfers for multiple, different IO configurations, which include variable packet sizes and/or variable/different numbers of transactions on the IO link. PCI Express protocol is enhanced to support utilization of counters and dynamically variable queue sizes. In addition to the standard queue entries, several (or a selected number of) dynamically changeable queue entries are provided/reserved and a dynamic queue modification (DQM) utility is provided within the enhanced PCI Express protocol to monitor ongoing, current data transfer and manage when the size(s) of the queue entries are modified (increased or decreased) based on current data traffic transmitting on the PCI Express IO link. The enhanced PCI Express protocol provides an equilibrium point at which many large data packets are transferred efficiently, while imposing a limit on the number of each size of packets outstanding. | 12-11-2008 |
20080313240 | Method for Creating Data Transfer Packets With Embedded Management Information - In a method of communicating management information from a completing entity to a requesting entity in a digital communication system, the availability of management information to be sent from the completing entity to the requesting entity is detected when generating a data packet that does not have a primary purpose of transmitting management information. The management information is included in a management information data field and the management information data field is appended to the data packet. The data packet and the management information are transmitted from the completing entity to the requesting entity. | 12-18-2008 |
20090094385 | Techniques for Handling Commands in an Ordered Command Stream - A technique for handling commands includes assigning respective first tags to ordered commands included in an ordered command stream. Respective second tags are then assigned to subsequent commands that follow an initial command (included in the ordered commands). Each of the respective second tags correspond to one the respective first tags that is associated with an immediate previous one of the ordered commands. The initial command is sent to an execution engine in a first cycle. At least one of the subsequent commands is sent to the execution engine prior to completion of execution of the initial command. | 04-09-2009 |
20090125666 | DYNAMICALLY SCALABLE QUEUES FOR PERFORMANCE DRIVEN PCI EXPRESS MEMORY TRAFFIC - A computer program product for implementing a method within a data processing system and a PCI Express protocol for enabling high performance IO data transfers for multiple, different IO configurations, which include variable packet sizes and/or variable/different numbers of transactions on the IO link. PCI Express protocol is enhanced to support utilization of counters and dynamically variable queue sizes. In addition to the standard queue entries, several (or a selected number of) dynamically changeable queue entries are provided/reserved and a dynamic queue modification (DQM) utility is provided within the enhanced PCI Express protocol to monitor ongoing, current data transfer and manage when the size(s) of the queue entries are modified (increased or decreased) based on current data traffic transmitting on the PCI Express IO link. The enhanced PCI Express protocol provides an equilibrium point at which many large data packets are transferred efficiently, while imposing a limit on the number of each size of packets outstanding. | 05-14-2009 |
20110225465 | Managing Memory Refreshes - Systems and methods to manage memory refreshes at a memory controller are disclosed. A method includes determining, at a memory controller device, that a number of transmission errors between a memory controller port and a memory redrive device exceeds an error threshold. The method may include initiating a first link retraining process between the memory controller port and the memory redrive device. The method may further include placing one or more dynamic random access memory modules associated with the memory redrive device in a self-refresh mode. The method may also include removing the one or more dynamic random access memory modules from the self-refresh mode after the link retraining process has completed. The method may further include enabling overlapping refreshes of the one or more dynamic random access memory modules. | 09-15-2011 |
20110320671 | MOVING OWNERSHIP OF A DEVICE BETWEEN COMPUTE ELEMENTS - In an embodiment, a command is received that requests movement of ownership of a target device from an origin compute element to a destination compute element. From the origin compute element, a translation of a virtual bridge identifier to a first secondary bus identifier, a first subordinate bus identifier, and a first MMIO bus address range is removed. To the destination compute element, a translation of the target virtual bridge identifier to a second secondary bus identifier, a second subordinate bus identifier, and a second MMIO bus address range is added. From a south chip that comprises the target virtual bridge, a translation of the target virtual bridge identifier to an identifier of the origin compute element is removed. To the south chip, a translation of the target virtual bridge identifier to an identifier of the destination compute element is added. | 12-29-2011 |
20120011283 | Transmitting Retry Request Associated With Non-Posted Command Via Response Credit Channel - In a particular embodiment, a method is disclosed that includes, at a first computing device coupled to a second computing device via a bus, receiving a request from the second computing device to complete a non-posted command, where the request is received via a request credit channel of the bus, and where the first computing device is configured to receive requests to complete non-posted commands and requests to complete posted commands via the request credit channel. The method also includes removing the request to complete the non-posted command from the request credit channel. The method further includes transmitting a retry request associated with the non-posted command to the second computing device via a response credit channel of the bus. | 01-12-2012 |
20120311221 | USING A PCI STANDARD HOT PLUG CONTROLLER TO MODIFY THE HIERARCHY OF A DISTRIBUTED SWITCH - The standard hot-plug controller (SHPC) specification may be used to generate PCI messages in a distributed switch to disconnect and/or connect virtual hierarchies of an endpoint from hosts that are connected based on multi-root input/output virtualization (MR-IOV). A management controller may instruct a SHPC to generate a PCI packet that specifies a particular virtual hierarchy to disconnect from a particular host. An upstream port connected to the host and the SHPC receives the PCI packet and uses a header that identifies the virtual endpoint in the packet to index into a routing table to identify a downstream port in the distributed switch that is connected to the endpoint. Once the PCI packet traverses the switch and arrives at the downstream port, the downstream port changes routing logic which logically disconnects the host from the specified virtual hierarchy. | 12-06-2012 |
20130339825 | EXTERNAL SETTINGS THAT RECONFIGURE THE ERROR HANDLING BEHAVIOR OF A DISTRIBUTED PCIE SWITCH - Method for performing an operation to maintain data integrity in a parallel computing system, the operation comprising providing a lookup table specifying a plurality of predefined destinations for data packets, receiving a first data packet comprising a destination address specifying a first destination, wherein the first data packet has an error of a first type, identifying, from the lookup table, an entry specifying a second destination for data packets having errors of the first type, and sending the first data packet to the second destination to avoid corrupting the first destination. | 12-19-2013 |
20130339826 | EXTERNAL SETTINGS THAT RECONFIGURE THE ERROR HANDLING BEHAVIOR OF A DISTRIBUTED PCIe SWITCH - Method, computer program product, and system for performing an operation to maintain data integrity in a parallel computing system, the operation comprising providing a lookup table specifying a plurality of predefined destinations for data packets, receiving a first data packet comprising a destination address specifying a first destination, wherein the first data packet has an error of a first type, identifying, from the lookup table, an entry specifying a second destination for data packets having errors of the first type, and sending the first data packet to the second destination to avoid corrupting the first destination. | 12-19-2013 |
20130346653 | VERSATILE LANE CONFIGURATION USING A PCIE PIE-8 INTERFACE - Each PCIe device may include a media access control (MAC) interface and a physical (PHY) interface that support a plurality of different lane configurations. These interfaces may include hardware modules that support 1×32, 2×16, 4×8, 8×4, 16×2, and 32×1 communication. Instead of physically connecting each of the hardware modules in the MAC interface to respective hardware modules in the PHY interface using dedicated traces, the device may include two bus controllers that arbitrate which hardware modules are connected to a internal bus coupling the two interfaces. When a different lane configuration is desired, the bus controller couples the corresponding hardware module to the internal bus. In this manner, the different lane configurations share the same lanes (and wires) of the bus as the other lane configurations. Accordingly, the shared bus only needs to include enough lanes (and wires) necessary to accommodate the widest lane configuration. | 12-26-2013 |
20130346662 | USING A PCI STANDARD HOT PLUG CONTROLLER TO MODIFY THE HIERARCHY OF A DISTRIBUTED SWITCH - The standard hot-plug controller (SHPC) specification may be used to generate PCI messages in a distributed switch to disconnect and/or connect virtual hierarchies of an endpoint from hosts that are connected based on multi-root input/output virtualization (MR-IOV). A management controller may instruct a SHPC to generate a PCI packet that specifies a particular virtual hierarchy to disconnect from a particular host. An upstream port connected to the host and the SHPC receives the PCI packet and uses a header that identifies the virtual endpoint in the packet to index into a routing table to identify a downstream port in the distributed switch that is connected to the endpoint. Once the PCI packet traverses the switch and arrives at the downstream port, the downstream port changes routing logic which logically disconnects the host from the specified virtual hierarchy. | 12-26-2013 |
20130346665 | VERSATILE LANE CONFIGURATION USING A PCIE PIE-8 INTERFACE - Each PCIe device may include a media access control (MAC) interface and a physical (PHY) interface that support a plurality of different lane configurations. These interfaces may include hardware modules that support 1×32, 2×16, 4×8, 8×4, 16×2, and 32×1 communication. Instead of physically connecting each of the hardware modules in the MAC interface to respective hardware modules in the PHY interface using dedicated traces, the device may include two bus controllers that arbitrate which hardware modules are connected to a internal bus coupling the two interfaces. When a different lane configuration is desired, the bus controller couples the corresponding hardware module to the internal bus. In this manner, the different lane configurations share the same lanes (and wires) of the bus as the other lane configurations. Accordingly, the shared bus only needs to include enough lanes (and wires) necessary to accommodate the widest lane configuration. | 12-26-2013 |
20130346801 | BANDWIDTH LIMITING ON GENERATED PCIE PACKETS FROM DEBUG SOURCE - Method, circuit, and system for performing an operation for regulating bandwidth, the operation comprising receiving at a memory, debug data packets and functional data packets for transmittal on a shared bus. The operation then transmits, via the shared bus, the functional data packets and one or more of the debug data packets according to a predefined ratio of debug data packets to functional data packets. The operation then drops one or more of the received debug data packets at the memory, and maintains a count of the one or more dropped debug data packets. The operation then updates the predefined ratio based on the count, and uses the updated predefined ratio to transmit the functional data packets and one or more of the debug data packets. | 12-26-2013 |
20130346802 | BANDWIDTH LIMITING ON GENERATED PCIE PACKETS FROM DEBUG SOURCE - Method, circuit, and system for performing an operation for regulating bandwidth, the operation comprising receiving at a memory, debug data packets and functional data packets for transmittal on a shared bus. The operation then transmits, via the shared bus, the functional data packets and one or more of the debug data packets according to a predefined ratio of debug data packets to functional data packets. The operation then drops one or more of the received debug data packets at the memory, and maintains a count of the one or more dropped debug data packets. The operation then updates the predefined ratio based on the count, and uses the updated predefined ratio to transmit the functional data packets and one or more of the debug data packets. | 12-26-2013 |