# Ron M. Roth, Haifa IL

## Ron M. Roth, Haifa IL

Patent application number | Description | Published |
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20100091662 | Defect-tolerant demultiplexers based on threshold logic - Embodiments of the present invention include defect-tolerant demultiplexer crossbars that employ, or that can be modeled by demultiplexer crossbars that employ, threshold logic “TL” elements. The threshold-logic elements provide for tolerance for signal variation on internal signals lines of a defect-tolerant demultiplexer crossbar, and thus tolerance for defects which produce internal signal variation. | 04-15-2010 |

20100299575 | METHOD AND SYSTEM FOR DETECTION AND CORRECTION OF PHASED-BURST ERRORS, ERASURES, SYMBOL ERRORS, AND BIT ERRORS IN A RECEIVED SYMBOL STRING - Embodiments of the present invention include ECC-based encoding-and-decoding schemes that are well suited for correcting phased bursts of errors or erasures as well as additional symbol errors and bit errors. Each encoding-and-decoding scheme that represents an embodiment of the present invention is constructed from two or more component error-correcting codes and a mapping function ƒ(). The composite error-correcting codes that represent embodiments of the present invention can correct longer phased bursts or a greater number of erasures in addition to single-bit errors and symbol errors, respectively, than either of the component codes alone, and are more efficient than previously developed ECC-based encoding-and-decoding schemes for correcting phased bursts of symbol errors and erasures combined with additional bit errors and symbol errors. | 11-25-2010 |

20120017136 | SYSTEMS AND METHODS FOR ENCODING INFORMATION FOR STORAGE IN AN ELECTRONIC MEMORY AND FOR DECODING ENCODED INFORMATION RETRIEVED FROM AN ELECTRONIC MEMORY - Method and system embodiments of the present invention are directed to encoding information in ways that are compatible with constraints associated with electrical-resistance-based memories and useful in other, similarly constrained applications, and to decoding the encoded information. One embodiment of the present invention encodes k information bits and writes the encoded k information bits to an electronic memory, the method comprising systematically encoding the k information bits to produce a vector codeword, with additional parity bits so that the codeword is resilient to bit-transition errors that may occur during storage of the codeword in, and retrieval of the codeword from, the electronic memory, ensuring that the codeword does not violate a weight constraint, and writing the codeword to the electronic memory. | 01-19-2012 |

20120087381 | APPROXIMATE ENUMERATIVE CODING METHOD AND APPARATUS - An approximate enumerative coding method ( | 04-12-2012 |

20120117431 | EFFICIENT DETECTION OF ERRORS IN ASSOCIATIVE MEMORY - A method for error detection includes storing in an associative memory ( | 05-10-2012 |

20120324140 | CODING FOR CROSSBAR ARCHITECTURE - A method for encoding bits to be stored within a crossbar memory architecture performed by a physical computing system includes designating, with the physical computing system, a subset of crosspoints within a crossbar matrix, the crossbar matrix comprising a number of disjointed intersecting wire segments, the subset corresponding to a predetermined path through the crossbar matrix; and encoding, with the physical computing system, a number of data bits to be placed along the predetermined path; in which the encoding causes bits pertaining to at least one of the wire segments to be subject to a constraint when the data bits are placed along the predetermined path. | 12-20-2012 |

20130044011 | ENCODING DATA BASED ON WEIGHT CONSTRAINTS - A method for encoding data to be placed into a weight constrained memory array includes designating a set of crosspoints within a crossbar memory array as indicator crosspoints and a set of crosspoints within the memory array as data crosspoints, the set of indicator crosspoints selected so that a net number of times that each data crosspoint has been flipped can be determined from a subset of the set of indicator crosspoints, placing an input stream of data into a matrix corresponding to crosspoints within the memory array, bits of the input stream being placed into matrix elements that correspond to data crosspoints of the memory array, setting each matrix element corresponding to indicator crosspoints to a value corresponding to a fixed resistive state, and flipping each bit corresponding to a conductor of the memory array until no conductors within the memory array violate a weight constraint. | 02-21-2013 |

20130097396 | METHOD AND SYSTEM FOR ENCODING DATA FOR STORAGE IN A MEMORY ARRAY - A method of storing data into a memory array converts an input string into a first binary array with (m−1) rows and (n−1) columns. A second binary array with m rows and n columns in an encoded bit pattern is then generated from the first binary array. The second binary array in the encoded bit pattern has at most n/2 1's in each row and at most m/2 1's in each column, and the m-th row and an n-th column contain information for decoding other entries of the second binary array. The encoded bit pattern of the second binary array is then stored into corresponding memory devices of the memory array. | 04-18-2013 |

20130100727 | OVERWRITING A MEMORY ARRAY - A data storage system including a memory array including a plurality of memory devices programmable in greater than two states. A read/write control module may overwrite data in the memory array without violating a constraint during the overwrite process. The memory array may be an m×n memory array. | 04-25-2013 |

20130103888 | MEMORY ARRAY INCLUDING MULTI-STATE MEMORY DEVICES - A data storage system including a memory array including a plurality of memory devices programmable in greater than two states. A memory control module may control operations of the memory array, and an encoder module may encode input data for storing to the memory array. The memory array may be an m×n memory array, and the memory control module may control operations of storing data to and retrieving data from the memory array. | 04-25-2013 |

20130262759 | Minimized Half-Select Current in Multi-State Memories - A multi-state memory system with encoding that minimizes half-select currents. The system includes an array of row and column conductors with a plurality of storage cells each capable of being placed into any of three or more physical states. An encoder is connected to receive data bits for storage and to apply activation signals to the row and column conductors to write information to the storage cells. The encoder is programmed to encode the data bits into entries in an array having one row corresponding with each row conductor and one column corresponding with each column conductor; select entries in the array according to half-select currents of the storage cells; apply a predetermined one-dimensional mapping that increases the value of at most one entry in the array to obtain a mapped array; and write entries of the mapped array into the storage cells. | 10-03-2013 |

20140211536 | INLINE FUSES IN PROGRAMMABLE CROSSBAR ARRAYS - A programmable crossbar array with inline fuses includes a layer of row lines and a layer of column lines with the row lines crossing over the column lines to form junctions and resistive memory elements sandwiched between row lines and a column lines at the junctions. Inline fuses are located in either the row lines, column lines or both. The inline fuses are interposed between the support circuitry and the resistive memory elements. A method for mitigating shorts in a crossbar array is also provided. | 07-31-2014 |

20140215121 | MEMORY CONTROLLER USING CRISSCROSS ERROR-CORRECTING CODES - A method is provided to manage access to a memory array. The method includes encoding a bit string with a rank metric encoder to generate an encoded binary array, modifying the encoded binary array so each row has at most half of the row with a bit value and each column has at most half of the column with the bit value, and storing the modified binary array into corresponding memory devices of the memory array. | 07-31-2014 |