Patent application number | Description | Published |
20110131231 | METHOD TO EFFICIENTLY LOCATE META-DATA STRUCTURES ON A FLASH-BASED STORAGE DEVICE - Flash memory systems and methods for efficiently locating meta-data structures on solid-state devices, such as, flash-based memory devices, which allows for fast reconstruction of metadata structures are provided. These systems and methods place checkpoints, which identify the location of metadata structures, intelligently on the device so as to permit a more efficient method of locating such checkpoints. These techniques ensure best wear-leveling as all blocks on the device undergo the same wear-leveling strategy. These systems and methods further provide a free block maintenance strategy that provides blocks freed by garbage collection for future checkpoint writes. | 06-02-2011 |
20110145475 | REDUCING ACCESS CONTENTION IN FLASH-BASED MEMORY SYSTEMS - Exemplary embodiments include a method for reducing access contention in a flash-based memory system, the method including selecting a chip stripe in a free state, from a memory device having a plurality of channels and a plurality of memory blocks, wherein the chip stripe includes a plurality of pages, setting the ship stripe to a write state, setting a write queue head in each of the plurality of channels, for each of the plurality of channels in the flash stripe, setting a write queue head to a first free page in a chip belonging to the channel from the chip stripe, allocating write requests according to a write allocation scheduler among the channels, generating a page write and in response to the page write, incrementing the write queue head, and setting the chip stripe into an on-line state when it is full. | 06-16-2011 |
20110202708 | Integrating A Flash Cache Into Large Storage Systems - An I/O enclosure module is provided with one or more I/O enclosures having a plurality of slots for receiving electronic devices. A host adapter is connected a first slot of the I/O enclosure module and is configured to connect a host to the I/O enclosure. A device adapter is connected to a second slot of the I/O enclosure module and is configured to connect a storage device to the I/O enclosure module. A flash cache is connected to a third slot of the I/O enclosure module and includes a flash-based memory configured to cache data associated with data requests handled through the I/O enclosure module. A primary processor complex manages data requests handled through the I/O enclosure module by communicating with the host adapter, device adapter, and flash cache to manage to the data requests. | 08-18-2011 |
20110296085 | CACHE MEMORY MANAGEMENT IN A FLASH CACHE ARCHITECTURE - Provided are a system, method, and computer program product for managing cache memory to cache data units in at least one storage device. A cache controller is coupled to at least two flash bricks, each comprising a flash memory. Metadata indicates a mapping of the data units to the flash bricks caching the data units, wherein the metadata is used to determine the flash bricks on which the cache controller caches received data units. The metadata is updated to indicate the flash brick having the flash memory on which data units are cached. | 12-01-2011 |
20120297128 | REDUCING ACCESS CONTENTION IN FLASH-BASED MEMORY SYSTEMS - Exemplary embodiments include a method for reducing access contention in a flash-based memory system, the method including selecting a chip stripe in a free state, from a memory device having a plurality of channels and a plurality of memory blocks, wherein the chip stripe includes a plurality of pages, setting the ship stripe to a write state, setting a write queue head in each of the plurality of channels, for each of the plurality of channels in the flash stripe, setting a write queue head to a first free page in a chip belonging to the channel from the chip stripe, allocating write requests according to a write allocation scheduler among the channels, generating a page write and in response to the page write, incrementing the write queue head, and setting the chip stripe into an on-line state when it is full. | 11-22-2012 |
20130145089 | CACHE MEMORY MANAGEMENT IN A FLASH CACHE ARCHITECTURE - Provided is a method for managing cache memory to cache data units in at least one storage device. A cache controller is coupled to at least two flash bricks, each comprising a flash memory. Metadata indicates a mapping of the data units to the flash bricks caching the data units, wherein the metadata is used to determine the flash bricks on which the cache controller caches received data units. The metadata is updated to indicate the flash brick having the flash memory on which data units are cached. | 06-06-2013 |
20160070715 | STORING DATA IN A DISTRIBUTED FILE SYSTEM - A device for storing data in a distributed file system, the distributed file system including a plurality of deduplication storage devices, includes a determination unit configured to determine a characteristic of first data to be stored in the distributed file system; an identification unit configured to identify one of the deduplication storage devices of the distributed file system as deduplication storage device for the first data based on the characteristic of the first data; and a storing unit configured to store the first data in the identified deduplication storage device such that the first data and second data being redundant to the first data are deduplicatable within the identified deduplication storage device. | 03-10-2016 |
Patent application number | Description | Published |
20110246821 | RELIABILITY SCHEME USING HYBRID SSD/HDD REPLICATION WITH LOG STRUCTURED MANAGEMENT - In one embodiment, a method of storing data includes storing a first copy of data in a solid state memory and storing a second copy of the data in a hard disk drive memory substantially simultaneously with the storing the first copy. In another embodiment, a system for storing data includes a solid state memory, at least one hard disk drive memory, and a controller for controlling storage of data in the solid state memory and the hard disk drive memory. Other methods, systems, and computer program products are also described according to various embodiments. | 10-06-2011 |
20130111106 | PROMOTION OF PARTIAL DATA SEGMENTS IN FLASH CACHE | 05-02-2013 |
20130111131 | DYNAMICALLY ADJUSTED THRESHOLD FOR POPULATION OF SECONDARY CACHE | 05-02-2013 |
20130111133 | DYNAMICALLY ADJUSTED THRESHOLD FOR POPULATION OF SECONDARY CACHE | 05-02-2013 |
20130111134 | MANAGEMENT OF PARTIAL DATA SEGMENTS IN DUAL CACHE SYSTEMS | 05-02-2013 |
20130111146 | SELECTIVE POPULATION OF SECONDARY CACHE EMPLOYING HEAT METRICS | 05-02-2013 |
20130111160 | SELECTIVE SPACE RECLAMATION OF DATA STORAGE MEMORY EMPLOYING HEAT AND RELOCATION METRICS | 05-02-2013 |
20130185512 | MANAGEMENT OF PARTIAL DATA SEGMENTS IN DUAL CACHE SYSTEMS - For movement of partial data segments within a computing storage environment having lower and higher levels of cache by a processor, a whole data segment containing one of the partial data segments is promoted to both the lower and higher levels of cache. Requested data of the whole data segment is split and positioned at a Most Recently Used (MRU) portion of a demotion queue of the higher level of cache. Unrequested data of the whole data segment is split and positioned at a Least Recently Used (LRU) portion of the demotion queue of the higher level of cache. The unrequested data is pinned in place until a write of the whole data segment to the lower level of cache completes. | 07-18-2013 |
20130205077 | PROMOTION OF PARTIAL DATA SEGMENTS IN FLASH CACHE - For efficient track destage in secondary storage in a more effective manner, for temporal bits employed with sequential bits for controlling the timing for destaging the track in a primary storage, the temporal bits and sequential bits are transferred from the primary storage to the secondary storage. The temporal bits are allowed to age on the secondary storage. | 08-08-2013 |
20130232294 | ADAPTIVE CACHE PROMOTIONS IN A TWO LEVEL CACHING SYSTEM - Provided are a computer program product, system, and method for managing data in a first cache and a second cache. A reference count is maintained in the second cache for the page when the page is stored in the second cache. It is determined that the page is to be promoted from the second cache to the first cache. In response to determining that the reference count is greater than zero, the page is added to a Least Recently Used (LRU) end of an LRU list in the first cache. In response to determining that the reference count is less than or equal to zero, the page is added to a Most Recently Used (LRU) end of the LRU list in the first cache. | 09-05-2013 |
20130232295 | ADAPTIVE CACHE PROMOTIONS IN A TWO LEVEL CACHING SYSTEM - Provided are a computer program product, system, and method for managing data in a first cache and a second cache. A reference count is maintained in the second cache for the page when the page is stored in the second cache. It is determined that the page is to be promoted from the second cache to the first cache. In response to determining that the reference count is greater than zero, the page is added to a Least Recently Used (LRU) end of an LRU list in the first cache. In response to determining that the reference count is less than or equal to zero, the page is added to a Most Recently Used (LRU) end of the LRU list in the first cache. | 09-05-2013 |
20140181383 | RELIABILITY SCHEME USING HYBRID SSD/HDD REPLICATION WITH LOG STRUCTURED MANAGEMENT - In one embodiment, a method of managing data includes managing a first copy of data in a solid state memory using a controller of the solid state memory, and managing a second copy of the data in a hard disk drive memory using the controller. In another embodiment, a system for storing data includes a solid state memory, at least one hard disk drive memory, and a controller for controlling storage of data in both the solid state memory and the hard disk drive memory. Other methods, systems, and computer program products are also described according to various embodiments. | 06-26-2014 |
20140201448 | MANAGEMENT OF PARTIAL DATA SEGMENTS IN DUAL CACHE SYSTEMS - For movement of partial data segments within a computing storage environment having lower and higher levels of cache by a processor, a whole data segment containing one of the partial data segments is promoted to both the lower and higher levels of cache. Requested data of the whole data segment is split and positioned at a Most Recently Used (MRU) portion of a demotion queue of the higher level of cache. | 07-17-2014 |
20140359228 | CACHE ALLOCATION IN A COMPUTERIZED SYSTEM - A computerized system comprises a solid state memory and a controller adapted to use the solid state memory as a cache for the computerized system. The controller is adapted to add or to remove a chunk of data from the cache based on a detected frequency of occurrence of the chunk of data in the computerized system. | 12-04-2014 |
20150067294 | METHOD AND SYSTEM FOR ALLOCATING A RESOURCE OF A STORAGE DEVICE TO A STORAGE OPTIMIZATION OPERATION - Allocating a resource of a storage device to a storage optimization operation. An available resource of the storage device is monitored. Determining an allocation proportion of the resource allocated to the storage optimization operation, based on at least one of historical running information and a predicted value of a performance improvement caused by the storage optimization operation. Allocating the resource of the storage device to the storage optimization operation based on the available resource and the allocation proportion. | 03-05-2015 |
20150095561 | PROMOTION OF PARTIAL DATA SEGMENTS IN FLASH CACHE - For efficient track destage in secondary storage in a more effective manner, for temporal bits employed with sequential bits for controlling the timing for destaging the track in a primary storage, a preference of movement to lower speed cache level is implemented based on at least one of an amount of holes and a data heat metric. If a first bit has at least one of a lower amount of holes and a hotter data heat metric, it is moved to the lower speed cache level ahead of a second bit that has at least one of a higher amount of holes and a cooler data heat. If the first bit has a hotter data heat and greater than a predetermined number of holes, the first bit is discarded. | 04-02-2015 |
20150255155 | STORAGE DEVICE WITH 2D CONFIGURATION OF PHASE CHANGE MEMORY INTEGRATED CIRCUITS - A storage device, apparatus, and method to write and/or read data from such storage device. The storage device, comprises a channel controller and phase change memory integrated circuits (PCM ICs) arranged in sub-channels, wherein each of the sub-channels comprises several PCM ICs connected by at least one data bus line, which at least one data bus line connects to the channel controller. The channel controller is configured to write data to and/or read data from the PCM ICs according to a matrix configuration of PCM ICs, wherein: a number of columns of the matrix configuration respectively corresponds to a number of the sub-channels, the sub-channels forming a channel, and a number of rows of the matrix configuration respectively corresponds to a number of sub-banks, the sub-banks forming a bank, wherein each of the sub-banks comprises PCM ICs that belong, each, to distinct sub-channels of the sub-channels. | 09-10-2015 |
20150286580 | MANAGEMENT OF PARTIAL DATA SEGMENTS IN DUAL CACHE SYSTEMS - For movement of partial data segments within a computing storage environment having lower and higher levels of cache by a processor, a whole data segment containing one of the partial data segments is promoted to both the lower and higher levels of cache, including considering an Input/Output Performance (IOP) metric, a bandwidth metric, and a garbage collection metric, and a whole data segment is promoted containing the one of the partial data segments to both the lower and higher levels of cache. | 10-08-2015 |
20150294720 | STORAGE DEVICE WITH 2D CONFIGURATION OF PHASE CHANGE MEMORY INTEGRATED CIRCUITS - A storage device, apparatus, and method to write and/or read data from such storage device. The storage device, comprises a channel controller and phase change memory integrated circuits (PCM ICs) arranged in sub-channels, wherein each of the sub-channels comprises several PCM ICs connected by at least one data bus line, which at least one data bus line connects to the channel controller. The channel controller is configured to write data to and/or read data from the PCM ICs according to a matrix configuration of PCM ICs, wherein: a number of columns of the matrix configuration respectively corresponds to a number of the sub-channels, the sub-channels forming a channel, and a number of rows of the matrix configuration respectively corresponds to a number of sub-banks, the sub-banks forming a bank, wherein each of the sub-banks comprises PCM ICs that belong, each, to distinct sub-channels of the sub-channels. | 10-15-2015 |
20160004456 | SELECTIVE SPACE RECLAMATION OF DATA STORAGE MEMORY EMPLOYING HEAT AND RELOCATION METRICS - Space of a data storage memory of a data storage memory system is reclaimed by determining heat metrics of data stored in the data storage memory; determining relocation metrics related to relocation of the data within the data storage memory; determining utility metrics of the data relating the heat metrics to the relocation metrics for the data; and making the data whose utility metric fails a utility metric threshold, available for space reclamation. | 01-07-2016 |
Patent application number | Description | Published |
20150245785 | IMPEDANCE TECHNIQUES IN TISSUE-MASS DETECTION AND CHARACTERIZATION - A device is described for measuring electrical characteristics of biological tissues with plurality of electrodes and a processor controlling the stimulation and measurement in order to detect the presence of abnormal tissue masses in organs. Examples of suitable organs are the breast, skin, oral cavity, lung, liver, colon, rectum, cervix, and prostate and determine probability of tumors containing malignant cancer cells being present in tissue. The approach can also be applied to biopsied tissue samples. The device has the capability of providing the location of the abnormality. The method for measuring electrical characteristics includes placing electrodes and applying a voltage waveform in conjunction with a current detector. A mathematical analysis method is then applied to the collected data, which computes spectrum of frequencies and correlates magnitudes and phases with given algebraic conditions to determine mass presence and type. | 09-03-2015 |
20150272470 | ELECTRICAL IMPEDANCE TECHNIQUES IN TISSUE-MASS DETECTION AND CHARACTERIZATION - A device is described for measuring electrical characteristics of biological tissues with plurality of electrodes and a processor controlling the stimulation and measurement in order to detect the presence of abnormal tissue masses in organs. Examples of suitable organs are the breast, skin, oral cavity, lung, liver, colon, rectum, cervix, and prostate and determine probability of tumors containing malignant cancer cells being present in tissue. The approach can also be applied to biopsied tissue samples. The device has the capability of providing the location of the abnormality. The method for measuring electrical characteristics includes placing electrodes and applying a voltage waveform in conjunction with a current detector. A mathematical analysis method is then applied to the collected data, which computes spectrum of frequencies and correlates magnitudes and phases with given algebraic conditions to determine mass presence and type. | 10-01-2015 |