Patent application number | Description | Published |
20090134514 | METHOD FOR FABRICATING ELECTRICAL BONDING PADS ON A WAFER - A method for fabricating electrical bonding pads on one face of a wafer includes the production of electrically conductive areas and electrical connection branches connecting these conductive areas. A layer of mask material is deposited and openings are produced in this mask layer which extend above said conductive areas and at least some of which extend at least partly beyond the peripheral edges of the underlying conductive areas. Blocks made of a solder material are produces in the openings by electrodeposition in a bath. The mask material is then removed along with the connection branches. The wafer is passed through or placed in an oven so as to shape, on the conductive areas, the blocks into substantially domed electrical bonding pads. | 05-28-2009 |
20100244249 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a semiconductor die attached to a support having electrically conductive paths, the semiconductor die having a bond-pad electrically connected to the electrically a conductive path on the support by a wire-bond of a first metallic composition, the wire-bond and the bond-pad being coated with a protection layer of a second metallic composition. | 09-30-2010 |
20110018135 | METHOD OF ELECTRICALLY CONNECTING A WIRE TO A PAD OF AN INTEGRATED CIRCUIT CHIP AND ELECTRONIC DEVICE - A wire is electrically connected to an electrical bonding pad of an integrated circuit chip and electronic device through an intermediate electrical interconnect block that is interposed between the electrical bonding pad and one end of the electrical lead wire. | 01-27-2011 |
20110074536 | ELECTRONIC CIRCUIT WITH AN INDUCTOR - An electronic device which includes an electronic component having a substrate and a plurality of metal interconnection layers, the plurality of metal interconnection layers having a top surface. It further comprises a dielectric layer situated above said metal interconnection layers, a conductive layer situated above said dielectric layer, an inductor coil and a ground shield, the inductor coil being formed in the conductive layer and the ground shield being formed in a layer of said plurality of metal interconnection layers. | 03-31-2011 |
20110092000 | METHOD FOR MANUFACTURING AND TESTING AN INTEGRATED ELECTRONIC CIRCUIT - A method for manufacturing and for testing an integrated circuit, including the steps of forming, on the upper portion of the integrated circuit, a passivation layer including openings at the level of metal tracks of the last interconnect stack of the integrated circuit; forming, in the openings, first pads connected to second pads formed on the passivation layer by conductive track sections, the first pads being intended for the connection of the integrated circuit; testing the integrated circuit by bringing test tips in contact with the second pads; and eliminating at least a portion of at least one of the conductive track sections. | 04-21-2011 |
20110151657 | METHOD FOR FABRICATING ELECTRICAL BONDING PADS ON A WAFER - A method for fabricating electrical bonding pads on the electrical contact areas of a wafer includes producing first blocks made of a solder material, producing second blocks made of a solder material on these first blocks, and passing the blocks through an oven so as to shape the blocks into approximately domed electrical bonding pads. | 06-23-2011 |
20110227222 | SURFACE-MOUNTED ELECTRONIC COMPONENT - A surface-mounted electronic component including balls bonded to its front surface and, on the front surface, a protective resin layer having a thickness smaller than the ball height, wherein grooves extend in the resin layer between balls of the chip. | 09-22-2011 |
20110248397 | SEMICONDUCTOR DEVICE HAVING STACKED COMPONENTS - A semiconductor device includes at least one first component ( | 10-13-2011 |
20120020039 | SURFACE-MOUNTED SHIELDED MULTICOMPONENT ASSEMBLY - A surface-mounted shielded multicomponent assembly, comprising a wafer on which several electronic components are assembled; an insulating layer conformally deposited on the structure with a thickness smaller than the height of the electronic components, comprising at least one opening emerging on a contact of said wafer; a conductive shielding layer covering the insulating layer and said at least one opening; and a resin layer covering the conductive layer. | 01-26-2012 |
20120025348 | SEMICONDUCTOR DEVICE COMPRISING A PASSIVE COMPONENT OF CAPACITORS AND PROCESS FOR FABRICATION - A semiconductor device includes a wafer having a frontside and a backside. The wafer is formed from at least one integrated circuit chip having an electrical connection frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. A passive component including at least one conductive plate and a dielectric plate is positioned adjacent the integrated circuit chip. An encapsulation block embeds the integrated circuit chip and the passive component, the block having a frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. An electrical connection is made between the electrical connection frontside and the passive component. That electrical connection includes connection lines placed on the wafer frontside and wafer backside. The electrical connection further includes at least one via passing through the encapsulation block. | 02-02-2012 |
20120061849 | SEMICONDUCTOR COMPONENT AND DEVICE PROVIDED WITH HEAT DISSIPATION MEANS - A first component includes a slice formed from an integrated circuit chip having a front face and a rear face. An encapsulation block encapsulates the integrated circuit chip such that front and rear faces of the chip and front and rear faces of the encapsulation block are co-planar to form front and rear faces of the slice. Front and rear electrical connection networks are provided on the front and rear faces, respectively, with the electrical connection networks linked by electrical connection vias passing through the encapsulation block. A thermal transfer layer at least partially covers the rear face. A second component may be behind and at a distance from the first component. Connection elements interposed between the first component and the second component include both thermal connection elements in contact with the thermal transfer layer and electrical connection elements interconnecting the first and second components. | 03-15-2012 |
20120104454 | OPTICAL DEVICE, PROCESS FOR FABRICATING IT AND AN ELECTRONIC PACKAGE COMPRISING THIS OPTICAL DEVICE - An optical device includes at least one optical die ( | 05-03-2012 |
20120248625 | SEMICONDUCTOR PACKAGE COMPRISING AN OPTICAL SEMICONDUCTOR DEVICE - A semiconductor package includes a transmissive support plate and includes at least one elongate hole. An integrated circuit semiconductor device is mounted on a rear face of the support plate. The semiconductor device includes first and second optical elements oriented towards the rear face of the support plate, where the first and second optical elements are placed on either side of the elongate hole. An encapsulation material made of an opaque material encapsulates the semiconductor device and fills the elongate hole so as to form an optical insulation partition between the first and second optical elements. A cavity is left, however, between each optical element and a rear face of the support plate. | 10-04-2012 |
20130009173 | OPTICAL ELECTRONIC PACKAGE - An electronic package includes a substrate wafer having front and rear faces and a through passage having a front window and a blind cavity communicating laterally with the front window. A receiving integrated circuit chip is mounted on the rear face and includes an optical sensor situated opposite the blind cavity. A transparent encapsulant extends above the optical sensor and at least partially fills the through passage. An emitting integrated circuit chip, embedded in the transparent encapsulant, includes an optical emitter of luminous radiation. The emitting integrated circuit chip may be mounted to the front face or within the through passage to the receiving integrated circuit chip. The substrate wafer may further include a second through passage. The receiving integrated circuit chip further includes a second optical sensor situated opposite the second through passage. A cover plate is mounted to the front face at the second through passage. | 01-10-2013 |
20130012276 | OPTICAL ELECTRONIC PACKAGE - An electronic package includes a substrate wafer having front and rear faces. An emitting integrated circuit chip is mounted to the front face of the substrate wafer and includes a light radiation optical emitter. A receiving integrated circuit chip is also mounted to the front face of the substrate wafer and includes at least one light radiation optical sensor. A transparent encapsulant extends above the optical sensor and the optical emitter. An opaque encapsulant encapsulates the transparent encapsulant. The opaque encapsulant has a front window situated above the optical emitter and which is offset laterally relative to the optical sensor. The transparent encapsulant accordingly has an uncovered front face situated above the optical emitter and offset laterally relative to the optical sensor. The opaque encapsulant may include an additional front window. The receiving integrated circuit chip further includes a second optical sensor situated opposite the additional front window. | 01-10-2013 |
20130079068 | OPTICAL ELECTRONIC PACKAGE - A package includes a substrate with an attached emitting IC chip and receiving IC chip. The emitting IC chip includes an optical emitter, and the receiving IC chip includes a main optical sensor and a secondary optical sensor. A case is provided with a bottom portion and a peripheral wall portion to cover the IC chips, wherein the edge of the peripheral wall portion is mounted to the substrate. The bottom portion of the case includes a main opening above the main optical sensor and a secondary opening above the optical emitter. An opaque material is interposed between the case and the receiving IC chip to isolate the main optical sensor from the secondary optical sensor and delimiting a chamber containing the secondary optical sensor and the optical emitter. The chamber is optically isolated from the main optical sensor and main opening, and may be filled with a transparent material. | 03-28-2013 |
20130105982 | LAND GRID ARRAY SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURE | 05-02-2013 |
20130214425 | DUAL SIDE PACKAGE ON PACKAGE - An electronic package includes a substrate wafer with an interconnect network. A first chip is fixed to a front of the substrate, connected to the interconnect network and encapsulated by a body. A second chip is placed on a back side of the substrate wafer and connected to the interconnect network by back-side connection elements interposed between the back side of the substrate and a front side of the second chip. Front-side connection elements are placed on the front side of the substrate and connected to the interconnect network. The connection elements extend beyond the frontal face of the body. The package may be mounted on a board with an interposed thermally conductive material. | 08-22-2013 |
20130248887 | OPTICAL ELECTRONIC PACKAGE - An optical electronic package includes transmitting chip and a receiving chip fixed to a wafer. A transparent encapsulation structure is formed by a transparent plate and a transparent encapsulation block that are formed over the transmitter chip and at least a portion of the receiver chip, with the transparent encapsulation block embedding the transmitter chip. An opaque encapsulation block extends over the transparent plate and includes an opening that reveals a front area of the transparent plate. The front area is situated above an optical transmitter of the transmitting chip and is offset laterally relative to an optical sensor of the receiving chip. | 09-26-2013 |
20140057394 | METHOD FOR MAKING A DOUBLE-SIDED FANOUT SEMICONDUCTOR PACKAGE WITH EMBEDDED SURFACE MOUNT DEVICES, AND PRODUCT MADE - A manufacturing process includes forming a reconstituted wafer, including embedding semiconductor dice in a molding compound layer and forming through-wafer vias in the layer. A fan-out redistribution layer is formed on a front side of the wafer, with electrical traces interconnecting the dice, through-wafer vias, and contact pads positioned on the redistribution layer. Solder balls are positioned on the contact pads and a molding compound layer is formed on the redistribution layer, reinforcing the solder balls. A second fan-out redistribution layer is formed on a back side of the wafer, with electrical traces interconnecting back ends of the through-wafer vias and contact pads positioned on a back face of the second redistribution layer. Flip-chips and/or surface-mounted devices are coupled to the contact pads of the second redistribution layer and encapsulated in an underfill layer formed on the back face of the second redistribution layer. | 02-27-2014 |