Patent application number | Description | Published |
20080217672 | INTEGRATED CIRCUIT HAVING A MEMORY - An integrated circuit having a memory arrangement including capacitor elements and further capacitor elements is disclosed. One embodiment provides a substrate layer with contact pads and further contact pads; the capacitor elements being disposed in a first level on the substrate layer and connected with the contact pads; the further capacitor elements being disposed in a second level above the first level; contact elements being disposed between the capacitor elements and connected with the further contact pads; the further capacitor elements being disposed above the contact elements and being connected with the contact elements. | 09-11-2008 |
20080253160 | INTEGRATED CIRCUIT HAVING A MEMORY CELL ARRAY AND METHOD OF FORMING AN INTEGRATED CIRCUIT - An integrated circuit having a memory cell array and a method of forming an integrated circuit is disclosed. One embodiment provides bitlines running along a first direction, wordlines running along a second direction substantially perpendicular to the first direction, active areas and bitline contacts. The bitline contacts are arranged in columns extending in the second direction and in rows extending in the first direction. A distance between neighboring bitlines is DL, and a distance between neighboring bitline contacts is DC, DC being measured parallel to the first direction. The following relation holds: 1/2.25≦DL/DC≦1/1.75. | 10-16-2008 |
20080296737 | Methods for Manufacturing a Structure on or in a Substrate, Imaging Layer for Generating Sublithographic Structures, Method for Inverting a Sublithographic Pattern, Device Obtainable by Manufacturing a Structure - One possible embodiment is a method of manufacturing a structure on or in a substrate with the following steps | 12-04-2008 |
20080308870 | INTEGRATED CIRCUIT WITH A SPLIT FUNCTION GATE - An integrated circuit is disclosed. One embodiment provides a field-effect transistor including a gate electrode, a channel region and a first source/drain region. The gate electrode may include a main section determining a first flat band voltage between the gate electrode and the channel region and a first lateral section that is in contact with the main section and that determines a second flat band voltage between the gate electrode and the first source/drain region. The first and second flat band voltages differ by at least 0.1 eV. | 12-18-2008 |
20090033362 | Method for Forming a Structure on a Substrate and Device - In one aspect, a method of forming a structure on a substrate is disclosed. For example, the method includes forming a first mask layer and a second mask layer, modifying a material property in regions of the first and second mask layers, and forming the structure based on the modified regions. | 02-05-2009 |
20090053892 | Method of Fabricating an Integrated Circuit - A method of fabricating an integrated circuit, including the steps of forming a first mask layer in the form of a hard mask layer including a plurality of first openings and a second mask layer with at least one second opening which at least partially overlaps with one of the first openings, wherein the at least one second opening is generated lithographically; and at least two neighboring first openings are distanced from each other with a center to center pitch smaller than the resolution limit of the lithography used for generating the second opening. | 02-26-2009 |
20090075462 | Method of Fabricating a Semiconductor Device - The invention relates to a method of fabricating an integrated circuit, including the steps of providing at least one layer; performing a first implantation step, wherein particles are implanted into the layer under a first direction of incidence; performing a second implantation step, wherein particles are implanted into the layer under a second direction of incidence which is different from the first direction of incidence; performing a removal step, wherein the layer is partially removed depending on the local implant dose generated by the first and the second implantation step. | 03-19-2009 |
20090127608 | INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT - An integrated circuit including a memory cell array is shown. The memory cell array comprises word lines extending in a first direction and bit lines extending in a second direction intersecting the first direction and memory cells. The memory cells may include storage elements, bit line contacts for coupling a corresponding memory cell to a corresponding bit line. The bit line contacts are arranged in a checkerboard pattern with respect to the first direction, and the storage elements are arranged in a regular grid along the first and second directions, respectively. | 05-21-2009 |
20090127722 | Method for Processing a Spacer Structure, Method of Manufacturing an Integrated Circuit, Semiconductor Device and Intermediate Structure with at Least One Spacer Structure - Method for processing at least one spacer structure in a manufacturing process of a semiconductor device, wherein the at least one spacer structure is subjected to at least one etch process step with an isotropic component and the spacer structure comprises at least one point on the surface with a large solid angle opening towards the environment. Method of manufacturing an integrated circuit, including a regional removal of a spacer structure, wherein the removal is determined by a pattern density in the vicinity of the spacer structure. | 05-21-2009 |
20090206315 | INTEGRATED CIRCUIT INCLUDING U-SHAPED ACCESS DEVICE - An integrated circuit includes a first contact, a second contact, and a U-shaped access device coupled to the first contact and the second contact. The integrated circuit includes self-aligned dielectric material isolating the first contact from the second contact. | 08-20-2009 |
20090206316 | INTEGRATED CIRCUIT INCLUDING U-SHAPED ACCESS DEVICE - An integrated circuit includes a U-shaped access device and a first line coupled to a first side of the access device. The integrated circuit includes a contact coupled to a second side of the access device and self-aligned dielectric material isolating the first line from the contact. | 08-20-2009 |
20090218690 | Reduced-Stress Through-Chip Feature and Method of Making the Same - A feature is inscribed in a major surface of a microelectronic workpiece having a material property expressed as a reference coefficient value. The feature includes a first material having a first coefficient value for the material property and a second material having a second coefficient value for the material property. The first coefficient value is different from the reference coefficient value different from the first coefficient value and the second coefficient value is different from the first coefficient value. The first and second materials behave as an aggregate having an aggregate coefficient value for the material property between the first coefficient value and the reference coefficient value. | 09-03-2009 |
20090219496 | Methods of Double Patterning, Photo Sensitive Layer Stack for Double Patterning and System for Double Patterning - Double patterning a photo sensitive layer stack, is disclosed including providing a substrate being coated with a first and a second photo resist layer, exposing both photo resist layers by employing lithographic projection steps, wherein a second lithographic projection step illuminates a latent image with a focal depth at least partially covering the second photo resist layer. | 09-03-2009 |
20090315090 | Isolation Trenches with Conductive Plates - Methods of forming isolation trenches, semiconductor devices, structures thereof, and methods of operating memory arrays are disclosed. In one embodiment, an isolation trench includes a recess disposed in a workpiece. A conductive material is disposed in a lower portion of the channel. An insulating material is disposed in an upper portion of the recess over the conductive material. | 12-24-2009 |
20100048023 | Methods for Manufacturing a Structure on a Substrate and Intermediate Product - Among other implementations, a method for manufacturing a structure on a substrate is described wherein at least one carrier structure is positioned on a substrate and at least one spacer structure is positioned on the sidewalls of the at least one carrier structure, the at least one carrier structure or the at least one spacer structure is subsequently removed and before or after the removal of the at least one spacer structure or the removal of the at least one carrier structure, an etch resistant layer is positioned in at least one of the following regions: a region not covered by the at least one carrier structure, a region not covered by the at least one spacer structure and a region not covered by the at least one carrier structure and the at least one spacer structure. | 02-25-2010 |
20100058018 | Memory Scheduler for Managing Internal Memory Operations - An integrated circuit includes: a resistive memory having an array of resistive memory cells; a memory controller that controls operation of the resistive memory in accordance with external commands from an external device; and a memory scheduler coupled to the resistive memory and to the memory controller. The memory scheduler schedules internal maintenance operations within the resistive memory in response to trigger conditions indicated by at least one sensor signal or external command. The operation of the memory scheduler and performance of the internal maintenance operations are transparent to the external device and, optionally, transparent to the memory controller. | 03-04-2010 |
20100061145 | Phase Change Memory Cell with MOSFET Driven Bipolar Access Device - Embodiments are directed to memory devices comprising a bipolar junction transistor having an emitter, a base and a collector; a first side of a resistance changing memory element coupled to the emitter of the bipolar junction transistor; and a MOSFET coupled to the base of the bipolar junction transistor. | 03-11-2010 |
20100110753 | Ferroelectric Memory Cell Arrays and Method of Operating the Same - An integrated circuit includes a plurality of switching devices, wherein each device includes a gate dielectric capable of assuming at least a first and a second polarization state. The integrated circuit further includes an address circuit configured to control bit lines electrically coupled to first load regions of a load path of the switching devices and a word line electrically coupled to gate electrodes of the switching devices. The address circuit is configured to control a write cycle such that a first voltage is induced at the gate dielectrics of selected ones of the switching devices and a second voltage is induced at the gate dielectrics of non-selected ones of the switching devices. The first voltage suffices to switch the gate dielectrics of the selected devices from the first to the second polarization state and the second voltage does not suffice to switch the gate dielectrics of the non-selected devices. | 05-06-2010 |
20130193512 | Semiconductor Arrangement with Active Drift Zone - A semiconductor device arrangement includes a semiconductor layer and at least one series circuit with a first semiconductor device and a plurality of n second semiconductor devices, with n>1. The first semiconductor device has a load path and active device regions integrated in the semiconductor layer. Each second semiconductor device has active device regions integrated in the semiconductor layer and a load path between a first and second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each second semiconductor device has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. The arrangement further includes an edge termination structure. | 08-01-2013 |
20130193525 | Semiconductor Arrangement with Active Drift Zone - A semiconductor device arrangement includes a first semiconductor device having a load path and a plurality of second semiconductor devices, each having a load path between a first and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices, and one of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. Each of the second semiconductor devices has at least one device characteristic. At least one device characteristic of at least one of the second semiconductor devices is different from the corresponding device characteristic of others of the second semiconductor devices. | 08-01-2013 |
20130264654 | Integrated Switching Device with Parallel Rectifier Element - An integrated circuit includes a semiconductor body with a first semiconductor layer and a second semiconductor layer arranged adjacent the first semiconductor layer in a vertical direction of the semiconductor body. The integrated circuit further includes a switching device with a control terminal and a load path between a first load terminal and a second load terminal, and a rectifier element connected in parallel with at least one section of the load path. The switching device is integrated in the first semiconductor layer and the rectifier element is integrated in the second semiconductor layer. | 10-10-2013 |
20130307059 | Semiconductor Device and Method for Manufacturing a Semiconductor Device - A semiconductor device includes a first region of a first conductivity type and a body region of a second conductivity type, the first conductivity type being different from the second conductivity type. The body region is disposed on a side of a first surface of the semiconductor substrate. The semiconductor device further includes a plurality of trenches arranged in the first surface of the substrate, the trenches extending in a first direction having a component perpendicular to the first surface. Doped portions of the second conductivity type are adjacent to a lower portion of a sidewall of the trenches. The doped portions are electrically coupled to the body region via contact regions. The semiconductor device further includes a gate electrode disposed in an upper portion of the trenches. | 11-21-2013 |
20140015592 | INTEGRATED CIRCUIT WITH AT LEAST TWO SWITCHES - A circuit includes first and second semiconductor switches each having a load path and control terminal and their load paths connected in series. At least one of the first and second switches includes a first semiconductor device having a load path and a control terminal, the control terminal coupled to the control terminal of the switch. A plurality of second semiconductor devices each have a load path between a first load terminal and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. | 01-16-2014 |
20140016361 | Circuit Arrangement with a Rectifier Circuit - A rectifier circuit includes first and second load terminals, a first semiconductor device having a load path and configured to receive a drive signal, and a plurality of second semiconductor devices each having a load path and each configured to receive a drive signal. The load paths of the second semiconductor devices are connected in series, and connected in series to the load path of the first semiconductor device. A series circuit with the first semiconductor device and the second semiconductor devices is connected between the load terminals. Each of the second semiconductor devices is configured to receive as a drive voltage either a load-path voltage of at least one of the second semiconductor devices, or a load-path of at least the first semiconductor device. The first semiconductor device is configured to receive as a drive voltage a load-path-voltage of at least one of the second semiconductor devices. | 01-16-2014 |
20140016386 | Circuit Arrangement with a Rectifier Circuit - A circuit arrangement includes a rectifier circuit having a first and a second load terminal, a first semiconductor device having a load path and a control terminal and a plurality of n, with n>1, second semiconductor devices, each having a load path between a first load terminal and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. The series circuit with the first semiconductor device and the second semiconductor devices are connected between the load terminals of the rectifier circuit. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. | 01-16-2014 |
20140062544 | Semiconductor Device Arrangement with a First Semiconductor Device and with a Plurality of Second Semiconductor Devices - Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device. | 03-06-2014 |
20140062585 | Circuit Arrangement with a First Semiconductor Device and with a Plurality of Second Semiconductor Devices - A circuit arrangement includes a first semiconductor device having a load path and a number of second semiconductor devices. Each second semiconductor device has a control terminal and a load path between a first load terminal and a second load terminal. The second semiconductor devices have their load paths connected in series and connected in series with the load path of the first semiconductor device. Each of the second semiconductor devices has a load terminal of one of the first semiconductor device and of one of the second semiconductor devices associated thereto and a voltage limiting element coupled between the control terminal of one of the second semiconductor devices and the load terminal associated with that one of the second semiconductor devices. | 03-06-2014 |
20140103439 | Transistor Device and Method for Producing a Transistor Device - A transistor device includes at least one transistor cell. The at least one transistor cell includes a semiconductor fin, and a source region, a drain region, a drift region and a body region in the semiconductor fin. The body region is arranged adjacent the source region and the drift region in a first direction of the semiconductor fin. The source region is arranged adjacent the drift region in a second direction of the semiconductor fin and dielectrically insulated from the drift region by a dielectric layer. The drift region is arranged adjacent the drain region in the first direction and has a doping concentration lower than a doping concentration of the drain region. A gate electrode is adjacent the body region in a third direction of the semiconductor fin. | 04-17-2014 |
20140266131 | Power Converter Circuit - A power converter circuit includes an input and an output. A supply circuit is configured to receive an input signal from the input and to generate a number of supply signals from the input signal. A number of converter units are provided. Each of the plurality of converter units is configured to receive one of the plurality of supply signals and to output an output signal to the output. | 09-18-2014 |
20140319610 | Lateral Power Semiconductor Device and Method for Manufacturing a Lateral Power Semiconductor Device - A lateral power semiconductor device includes a semiconductor body having a first surface and a second opposite surface, a first main electrode, a second main electrode, a plurality of switchable semiconductor cells and at least one curved semiconductor portion. The first main electrode includes at least two sections and is arranged on the first surface. The second main electrode is arranged on the first surface and between the two sections of the first main electrode. The plurality of switchable semiconductor cells is arranged between a respective one of the two sections of the first main electrode and the second main electrode and is configured to provide a controllable conductive path between the first main electrode and the second main electrode. The curved semiconductor portion is between the first main electrode and the second main electrode and has increasing doping concentration from the first main electrode to the second main electrode. | 10-30-2014 |
20150035586 | SOLID-STATE SWITCHING DEVICE HAVING A HIGH-VOLTAGE SWITCHING TRANSISTOR AND A LOW-VOLTAGE DRIVER TRANSISTOR - According to an embodiment, a solid-state switching device includes a high-voltage switching transistor including a source, a drain and a gate, and being adapted for switching a high voltage on the basis of a switching signal, and a switching driver circuit operationally connected to the high-voltage switching transistor, the switching driver circuit including a low-voltage driver transistor including a source, a drain and a gate, connected in series to the high-voltage switching transistor and being adapted for transferring the switching signal to the high-voltage switching transistor, wherein the high-voltage switching transistor is arranged source-down on top of the drain of the low-voltage driver transistor. | 02-05-2015 |
20150041915 | Semiconductor Arrangement with Active Drift Zone - A semiconductor device arrangement includes a first semiconductor device having a load path and a plurality of second semiconductor devices, each having a load path between a first and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices, and one of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. Each of the second semiconductor devices has at least one device characteristic. At least one device characteristic of at least one of the second semiconductor devices is different from the corresponding device characteristic of others of the second semiconductor devices. | 02-12-2015 |