Patent application number | Description | Published |
20080242040 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE - A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature is formed over the substrate. The feature is substantially homogeneous in a lateral direction. A first ion implantation process adapted to introduce first dopant ions into at least one portion of the substrate adjacent the feature is performed. The length of the feature in the lateral direction is reduced. After the reduction of the length of the feature, a second ion implantation process adapted to introduce second dopant ions into at least one portion of the substrate adjacent the feature is performed. The feature may be a gate electrode of a field effect transistor to be formed over the semiconductor substrate. | 10-02-2008 |
20080268625 | ENHANCING TRANSISTOR CHARACTERISTICS BY A LATE DEEP IMPLANTATION IN COMBINATION WITH A DIFFUSION-FREE ANNEAL PROCESS - By combining an anneal process for adjusting the effective channel length and a substantially diffusion-free anneal process performed after a deep drain and source implantation, the vertical extension of the drain and source region may be increased substantially without affecting the previously adjusted channel length. In this manner, in SOI devices, the drain and source regions may extend down to the buried insulating layer, thereby reducing the parasitic capacitance, while the degree of dopant activation and thus series resistance in the extension regions may be improved. Furthermore, less critical process parameters during the anneal process for adjusting the channel length may provide the potential for reducing the lateral dimensions of the transistor devices. | 10-30-2008 |
20090004799 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE COMPRISING A FORMATION OF AT LEAST ONE SIDEWALL SPACER STRUCTURE - According to an illustrative example, a method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first feature and a second feature. A material layer is formed over the first feature and the second feature. A mask is formed over the first feature. At least one etch process adapted to form a sidewall spacer structure adjacent the second feature from a portion of the material layer is performed. The mask protects a portion of the material layer over the first feature from being affected by the at least one etch process. An ion implantation process is performed. The mask remains over the first feature during the ion implantation process. | 01-01-2009 |
20090170339 | REDUCING THE CREATION OF CHARGE TRAPS AT GATE DIELECTRICS IN MOS TRANSISTORS BY PERFORMING A HYDROGEN TREATMENT - By performing a heat treatment on the basis of a hydrogen ambient, exposed silicon-containing surface portions may be reorganized prior to the formation of gate dielectric materials. Hence, the interface quality and the material characteristics of the gate dielectrics may be improved, thereby reducing negative bias temperature instability effects in highly scaled P-channel transistors. | 07-02-2009 |
20090218601 | TEMPERATURE MONITORING IN A SEMICONDUCTOR DEVICE BY USING AN PN JUNCTION BASED ON SILICON/GERMANIUM MATERIAL - By incorporating germanium material into thermal sensing diode structures, the sensitivity thereof may be significantly increased. In some illustrative embodiments, the process for incorporating the germanium material may be performed with high compatibility with a process flow for incorporating a silicon/germanium material into P-channel transistors of sophisticated semiconductor devices. Hence, temperature control efficiency may be increased with reduced die area consumption. | 09-03-2009 |
20090218639 | SEMICONDUCTOR DEVICE COMPRISING A METAL GATE STACK OF REDUCED HEIGHT AND METHOD OF FORMING THE SAME - By providing a CMP stop layer in a metal gate stack, the initial height thereof may be efficiently reduced after the definition of the deep drain and source areas, thereby providing enhanced process conditions for forming highly stressed dielectric materials. Consequently, the dielectric material may be positioned more closely to the channel region substantially without deteriorating gate conductivity. | 09-03-2009 |
20100077839 | IN SITU MONITORING OF METAL CONTAMINATION DURING MICROSTRUCTURE PROCESSING - By providing a tool internal sensor device in a process tool in a semiconductor facility, metal contamination may be monitored in situ, thereby avoiding or at least significantly reducing the requirement for sophisticated sample preparation techniques, such as vapor phase decomposition tests in combination with subsequent analysis procedures. Thus, a full time inspection of process tools may be accomplished. | 04-01-2010 |
20100203698 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE - A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature is formed over the substrate. The feature is substantially homogeneous in a lateral direction. A first ion implantation process adapted to introduce first dopant ions into at least one portion of the substrate adjacent the feature is performed. The length of the feature in the lateral direction is reduced. After the reduction of the length of the feature, a second ion implantation process adapted to introduce second dopant ions into at least one portion of the substrate adjacent the feature is performed. The feature may be a gate electrode of a field effect transistor to be formed over the semiconductor substrate. | 08-12-2010 |
20110045665 | REDUCING THE CREATION OF CHARGE TRAPS AT GATE DIELECTRICS IN MOS TRANSISTORS BY PERFORMING A HYDROGEN TREATMENT - By performing a heat treatment on the basis of a hydrogen ambient, exposed silicon-containing surface portions may be reorganized prior to the formation of gate dielectric materials. Hence, the interface quality and the material characteristics of the gate dielectrics may be improved, thereby reducing negative bias temperature instability effects in highly scaled P-channel transistors. | 02-24-2011 |
20120025276 | TEMPERATURE MONITORING IN A SEMICONDUCTOR DEVICE BY USING A PN JUNCTION BASED ON SILICON/GERMANIUM MATERIALS - By incorporating germanium material into thermal sensing diode structures, the sensitivity thereof may be significantly increased. In some illustrative embodiments, the process for incorporating the germanium material may be performed with high compatibility with a process flow for incorporating a silicon/germanium material into P-channel transistors of sophisticated semiconductor devices. Hence, temperature control efficiency may be increased with reduced die area consumption. | 02-02-2012 |
20130075821 | Semiconductor Device Comprising Replacement Gate Electrode Structures and Self-Aligned Contact Elements Formed by a Late Contact Fill - When forming self-aligned contact elements in sophisticated semiconductor devices in which high-k metal gate electrode structures are to be provided on the basis of a replacement gate approach, the self-aligned contact openings are filled with an appropriate fill material, such as polysilicon, while the gate electrode structures are provided on the basis of a placeholder material that can be removed with high selectivity with respect to the sacrificial fill material. In this manner, the high-k metal gate electrode structures may be completed prior to actually filling the contact openings with an appropriate contact material after the removal of the sacrificial fill material. In one illustrative embodiment, the placeholder material of the gate electrode structures is provided in the form of a silicon/germanium material. | 03-28-2013 |
20130115773 | Prevention of ILD Loss in Replacement Gate Technologies by Surface Treatmen - When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, pronounced loss of the interlayer dielectric material may be avoided by inserting at least one surface modification process, for instance in the form of a nitridation process. In this manner, leakage paths caused by metal residues formed in the interlayer dielectric material may be significantly reduced. | 05-09-2013 |
20130168773 | High-K Metal Gate Electrode Structure Formed by Removing a Work Function on Sidewalls in Replacement Gate Technology - When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, the fill conditions upon filling in the highly conductive electrode metal, such as aluminum, may be enhanced by removing the final work function metal, for instance a titanium nitride material in P-channel transistors, only preserving a well-defined bottom layer. | 07-04-2013 |
20140113419 | METHODS OF REDUCING MATERIAL LOSS IN ISOLATION STRUCTURES BY INTRODUCING INERT ATOMS INTO OXIDE HARD MASK LAYER USED IN GROWING CHANNEL SEMICONDUCTOR MATERIAL - In one example, the method includes forming a plurality of isolation structures in a semiconducting substrate that define first and second active regions where first and second transistor devices, respectively, will be formed, forming a hard mask layer on a surface of the substrate above the first and second active regions, wherein the hard mask layer comprises at least one of carbon, fluorine, xenon or germanium ions, performing a first etching process to remove a portion of the hard mask layer and expose a surface of one of the first and second active regions, after performing the first etching process, forming a channel semiconductor material on the surface of the active region that was exposed by the first etching process, and after forming the channel semiconductor material, performing a second etching process to remove remaining portions of the hard mask layer that were not removed during the first etching process. | 04-24-2014 |