Patent application number | Description | Published |
20080198653 | CIRCUIT ARRANGEMENT AND METHOD FOR OPERATING A CIRCUIT ARRANGEMENT - A circuit arrangement includes a nonvolatile memory cell having a continuously variable characteristic that can be read out. A programming unit is coupled to the memory cell and designed to apply an analog signal to the memory cell in order to vary the characteristic, if the characteristic lies within a predetermined range of values, in such a way that the characteristic lies outside the predetermined range of values. A supply voltage unit is provided for providing a supply voltage. A changeover unit is coupled to the supply voltage unit and to the programming unit and designed to trigger the application of the analog signal to the memory cell if the supply voltage is interrupted. | 08-21-2008 |
20090040803 | Semiconductor Memory and Method for Operating a Semiconductor Memory - A semiconductor memory having read amplifier strips having a plurality of read amplifiers and having memory cell fields which have a plurality of memory cells connected to bit lines is disclosed. The read amplifier strips include at least two outer read amplifier strips between which the remaining read amplifier strips and the memory cell fields are arranged, wherein adjacent to at least one of the outer read amplifier strips, a reference circuit field is arranged, which has reference lines and reference circuit elements connected thereto, and wherein the reference lines are shorter than the bit lines of the memory cell fields. | 02-12-2009 |
20090285006 | Semiconductor Memory and Method for Operating a Semiconductor Memory - A semiconductor memory has a plurality of read amplifiers to which a pair each of two complementary bit lines is connected, wherein the semiconductor memory includes at least one switching element each for each bit line, by which at least a partial section of the bit line may be electrically decoupled from the read amplifier, and wherein the semiconductor memory controls the first switching element so that the first switching element, when reading out and/or refreshing any memory cell connected to the bit line, temporarily electrically decouples at least the partial section of the bit line from the read amplifier. | 11-19-2009 |
20100054022 | Method and Apparatus for Reducing Charge Trapping in High-K Dielectric Material - In one embodiment, an integrated circuit includes a memory array having a plurality of capacitors for storing data of an initial state in the memory array in an initial state. The integrated circuit also includes circuitry for occasionally inverting the data stored by the plurality of capacitors and tracking whether the current state of the data stored by the plurality of capacitors corresponds to the initial state. The circuitry inverts the data read out of the memory array during a read operation when the current state of the data does not correspond to the initial state. | 03-04-2010 |
Patent application number | Description | Published |
20080197430 | Biochemical Semiconductor Chip Laboratory Comprising A Coupled Address And Control Chip And Method For Producing The Same - A biochemical semiconductor chip laboratory is disclosed including a coupled address and control chip for biochemical analyses and a method for producing the same. In at least one embodiment the semiconductor chip laboratory has a semiconductor sensor chip, which provides numerous analytical positions for biochemical samples in a matrix. The sensor chip is located on the address and control chip and the analytical positions are in electric contact with a printed contact structure on the upper face of the address and control chip via low-resistance through-platings through the semiconductor substrate of the semiconductor chip. | 08-21-2008 |
20080259665 | Rectifier Circuit, Circuit Arrangement and Method for Manufactiring a Rectifier Circuit - One aspect of the invention relates to a rectifier circuit for providing a rectified voltage, with a first AC voltage terminal to which an AC voltage can be applied, with a first DC voltage terminal to which a DC voltage can be provided, and with a control switching element between the first AC voltage terminal and the first DC voltage terminal. The control switching element only couples the first AC voltage terminal to the first DC voltage terminal if the electrical potential at the first AC voltage terminal has a predeterminable polarity compared with a reference potential and if the amount of the electrical potential at the first DC voltage terminal is less than or equal to the amount of the electrical potential at the first AC voltage terminal. | 10-23-2008 |
20090322371 | Measuring Arrangement, Semiconductor Arrangement and Method for Operating a Semiconductor Component as a Reference Source - The invention relates to a measuring arrangement, a semiconductor arrangement and a method for operating a reference source, wherein at least one semiconductor component and a voltage source are connected to a measuring unit and the measuring unit provides a measured value that is proportional to the number of defects. | 12-31-2009 |
20090322404 | Arrangement, Use of an Arrangement, Reference Voltage Source and Method for Generating a Voltage Value Linearly Proportional to the Temperature - The invention relates to an arrangement comprising a logarithmizing unit and a subtracting unit, wherein the subtracting unit has an output at which a voltage value linearly proportional to the temperature can be tapped off. | 12-31-2009 |
Patent application number | Description | Published |
20120275252 | DIFFERENTIAL SENSE AMPLIFIER WITHOUT SWITCH TRANSISTORS - A differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line (BL) and an input connected to a second bit line complementary to the first bit line and a second CMOS inverter having an output connected to the second bit line (/BL) and an input connected to the first bit line. Each CMOS inverter includes pull-up and pull-down transistors, wherein the sources of either of the pull-up transistors or the pull-down transistors are electrically coupled and connected to a pull-up voltage source or a pull-down voltage source without an intermediate transistor between the sources of the transistors and the voltage source. | 11-01-2012 |
20120275253 | DIFFERENTIAL SENSE AMPLIFIER WITHOUT DEDICATED PASS-GATE TRANSISTORS - A differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line and an input connected to a second bit line complementary to the first bit line, and a second CMOS inverter having an output connected to the second bit line and an input connected to the first bit line. Each CMOS inverter includes a pull-up transistor and a pull-down transistor, and the sense amplifier has a pair of pass-gate transistors arranged to connect the first and second bit lines to a first and a second global bit lines. Advantageously, the pass-gate transistors are constituted by the pull-up transistors or the pull-up transistors. | 11-01-2012 |
20120275254 | DIFFERENTIAL SENSE AMPLIFIER WITHOUT DEDICATED PRECHARGE TRANSISTORS - The invention relates to a differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line and an input connected to a second bit line complementary to the first bit line, and a second CMOS inverter having an output connected to the second bit line and an input connected to the first bit line (BL). Each CMOS inverter includes a pull-up transistor and a pull-down transistor, with the sense amplifier having a pair of precharge transistors arranged to be respectively coupled to the first and second bit lines, to precharge the first and second bit lines to a precharge voltage. The precharge transistors are constituted by the pull-up transistors or by the pull-down transistors. | 11-01-2012 |
20140321225 | SENSE AMPLIFIER WITH DUAL GATE PRECHARGE AND DECODE TRANSISTORS - The invention relates to a sense amplifier for sensing and amplifying data stored in a memory cell, the sense amplifier being connected between a bit line (BL) and a reference bit line complementary (/BL) to the first bit line and comprising: a sense circuit (SC) capable of providing an output indicative of the data stored in the memory cell; and a precharge and decode circuit (PDC) comprising a pair of dual gate transistors (T | 10-30-2014 |
20140376318 | CIRCUIT AND METHOD FOR SENSING A DIFFERENCE IN VOLTAGE ON A PAIR OF DUAL SIGNAL LINES, IN PARTICULAR THROUGH EQUALIZE TRANSISTOR - a circuit for sensing a difference in voltage on a pair of dual signal lines comprising a first signal line and a second signal line complementary to the first signal line, comprising:
| 12-25-2014 |