| Patent application number | Description | Published |
|---|
| 20090075622 | OFFSET CORRECTION FOR PASSIVE MIXERS - A downconversion mixer includes a configurable gate or bulk bias voltage to allow calibration and correction of device offsets. Calibration may be performed on the configurable bias voltages to minimize IM2 distortion in the mixer. The techniques have minimal impact on voltage headroom, impose no requirement for a signal path to be phase-matched with a calibration path, and are particularly well-suited for passive mixers. | 03-19-2009 |
| 20090160704 | NAVIGATION RECEIVER - The subject matter disclosed herein relates to a system and method for processing navigation signals received from multiple global navigation satellite systems (GNSS′). In a particular implementation, signals received from multiple GNSS′ may be processed in a single receiver channel. | 06-25-2009 |
| 20090298422 | Calibration Using Noise Power - A method calibrates a spread spectrum receiver having a received signal strength below a noise floor. The method includes estimating an input noise power, and measuring a noise power output from the receiver. The method also includes comparing the estimated input noise power with the measured output noise power to determine at least one calibration value. The method further includes calibrating the receiver based upon the at least one calibration value. | 12-03-2009 |
| 20100007424 | METHOD OF ACHIEVING HIGH SELECTIVITY IN RECEIVER RF FRONT-ENDS - According to some embodiments, an apparatus may comprise an amplifier, wherein the amplifier comprises: an output stage formed of a positive output terminal providing a positive output voltage and a negative output terminal providing a negative output voltage; a load tank coupled in parallel with the output stage and configured to filter signals received at the amplifier; and a negative resistance block coupled in parallel with the output stage and the load tank. | 01-14-2010 |
| 20100085090 | CLOCK CLEAN-UP PHASE-LOCKED LOOP (PLL) - A clock clean-up phase-locked loop (PLL) that may reduce spurs and improve performance of a receiver is described. In one exemplary design, an integrated circuit includes a PLL and an analog-to-digital converter (ADC). The PLL receives a first clock signal generated with a fractional divider ratio and having spurs due to abrupt frequency jumps. The first clock signal may be generated by a fractional-N frequency synthesizer external to the integrated circuit. The PLL generates a second clock signal with an integer divider ratio and having reduced spurs. The ADC digitizes an analog baseband signal based on the second clock signal and provides digital samples. The integrated circuit may further include a low noise amplifier (LNA), which may observe less spurs coupled via the substrate of the integrated circuit due to the use of the PLL to clean up the first clock signal. | 04-08-2010 |
| 20100099372 | TUNABLE FILTERS WITH LOWER RESIDUAL SIDEBAND - An apparatus includes first and second filters and a bandwidth control circuit. The first filter operates as part of a first oscillator in a first mode and filters a first input signal and provides a first output signal in a second mode. The second filter operates as part of a second oscillator in the first mode and filters a second input signal and provides a second output signal in the second mode. The bandwidth control circuit adjusts the bandwidth of the first and second filters in the first mode, e.g., adjusts the oscillation frequency of each oscillator to obtain a target bandwidth for an associated filter. The apparatus may further include first and second gain control circuits. Each gain control circuit may vary the amplitude of an oscillator signal from an associated oscillator and/or set a gain of an associated filter in the first mode. | 04-22-2010 |
| 20100156532 | CLASS AB AMPLIFIER WITH RESISTIVE LEVEL-SHIFTING CIRCUITRY - A class AB amplifier with resistive level-shifting circuitry is described. In one exemplary design, the class AB amplifier includes an input stage, a resistive level-shifting stage, a class AB output stage, and a bias circuit. The input stage receives an input signal and provides a first drive signal. The resistive level-shifting stage receives the first drive signal and provides a second drive signal. The output stage receives the first and second drive signals and provides an output signal. The bias circuit generates a bias voltage for the resistive level-shifting stage to obtain a desired quiescent current for the output stage. In one exemplary design, the resistive level-shifting stage includes a transistor and a resistor. The transistor receives the bias voltage and provides the second drive signal. The resistor is coupled to the transistor and provides a voltage drop between the first and second drive signals. | 06-24-2010 |
| 20100265875 | HYBRID MULTI-BAND RECEIVER - The subject matter disclosed herein relates to a system and method for processing wireless signals received from one or more communications systems. In a particular implementation, one or more signals received from one or more communication systems such as a GNSS may be processed in two or more separate wireless signal receiver paths and combined in baseband to share one analog-to-digital converter. | 10-21-2010 |
