| Patent application number | Description | Published |
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| 20090001464 | FINFET WITH TOP BODY CONTACT - FinFETs are provided with a body contact on a top surface of a semiconductor fin. The top body contact may be self-aligned with respect to the semiconductor fin and the source and drain regions. Alternately, the source and drain regions may be formed recessed from the top surface of the semiconductor fin. The body or an extension of the body may be contacted above the channel or above one of the source and drain regions. Electrical shorts between the source and drain and the body contacts are avoided by the recessing of the source and drain regions from the top surface of the semiconductor fin. | 01-01-2009 |
| 20090026491 | TUNNELING EFFECT TRANSISTOR WITH SELF-ALIGNED GATE - In one embodiment, a mandrel and an outer dummy spacer may be employed to form a first conductivity type region. The mandrel is removed to form a recessed region wherein a second conductivity type region is formed. In another embodiment, a mandrel is removed from within shallow trench isolation to form a recessed region, in which an inner dummy spacer is formed. A first conductivity type region and a second conductivity region are formed within the remainder of the recessed region. An anneal is performed so that the first conductivity type region and the second conductivity type region abut each other by diffusion. A gate electrode is formed in self-alignment to the p-n junction between the first and second conductivity regions. The p-n junction controlled by the gate electrode, which may be sublithographic, constitutes an inventive tunneling effect transistor. | 01-29-2009 |
| 20090051002 | ELECTRICAL FUSE HAVING A THIN FUSELINK - A thin semiconductor layer is formed and patterned on a semiconductor substrate to form a thin semiconductor fuselink on shallow trench isolation and between an anode semiconductor region and a cathode semiconductor region. During metallization, the semiconductor fuselink is converted to a thin metal semiconductor alloy fuselink as all of the semiconductor material in the semiconductor fuselink reacts with a metal to form a metal semiconductor alloy. The inventive electrical fuse comprises the thin metal semiconductor alloy fuselink, a metal semiconductor alloy anode, and a metal semiconductor alloy cathode. The thin metal semiconductor alloy fuselink has a smaller cross-sectional area compared with prior art electrical fuses. Current density within the fuselink and the divergence of current at the interface between the fuselink and the cathode or anode comparable to prior art electrical fuses are obtained with less programming current than prior art electrical fuses. | 02-26-2009 |
| 20090056998 | METHODS FOR MANUFACTURING A SEMI-BURIED VIA AND ARTICLES COMPRISING THE SAME - Disclosed herein is a method comprising drilling a first hole in a multilayered device; the multilayered device comprising a fill layer disposed between and in intimate contact with two layers of a first electrically conducting material; the fill layer being electrically insulating; plating the first hole with a slurry; the slurry comprising a magnetic material, an electrically conducting material, or a combination comprising at least one of the foregoing materials; filling the first hole with a fill material; the fill material being electrically insulating; laminating a first layer and a second layer on opposing faces of the multilayered device to form a laminate; the opposing faces being the faces through which the first hole is drilled; the first layer and the second layer each comprising a second electrically conducting material; drilling a second hole through the laminate; the second hole having a circumference that is encompassed by a circumference of the first hole; and plating the surface of the second hole with a third electrically conducting material. | 03-05-2009 |
| 20090101956 | EMBEDDED TRENCH CAPACITOR HAVING A HIGH-K NODE DIELECTRIC AND A METALLIC INNER ELECTRODE - A deep trench is formed in a semiconductor substrate and a pad layer thereupon, and filled with a dummy node dielectric and a dummy trench fill. A shallow trench isolation structure is formed in the semiconductor substrate. A dummy gate structure is formed in a device region after removal of the pad layer. A first dielectric layer is formed over the dummy gate structure and a protruding portion of the dummy trench fill and then planarized. The dummy structures are removed. The deep trench and a cavity formed by removal of the dummy gate structure are filled with a high dielectric constant material layer and a metallic layer, which form a high-k node dielectric and a metallic inner electrode of a deep trench capacitor in the deep trench and a high-k gate dielectric and a metal gate in the device region. | 04-23-2009 |
| 20090213565 | EMC SHIELDING FOR PRINTED CIRCUITS USING FLEXIBLE PRINTED CIRCUIT MATERIALS - Exemplary embodiments of the present invention relate to a method for making multilayer flexible printed circuit carrier. The method comprises producing a first flexible conductor layer having a first width, producing a second flexible conductor layer having a second width larger than the first width, and separating a first side of the first flexible conductor and a first side of the second flexible conductors with a first insulator. The method also comprises placing a second insulator over at least a portion of a second surface of the first flexible conductor, and wrapping a portion of the second flexible conductor over the at least a portion of the second surface of the first flexible conductor. | 08-27-2009 |
| 20090242953 | SHALLOW TRENCH CAPACITOR COMPATIBLE WITH HIGH-K / METAL GATE - Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well. | 10-01-2009 |
| 20090256211 | METAL GATE COMPATIBLE FLASH MEMORY GATE STACK - A first gate stack comprising two stacked gate electrodes in a first device region, a second gate stack comprising a metal gate electrode in a second device region, and a third gate stack comprising a semiconductor gate electrode in a third device region are formed by forming and removing portions of a silicon-oxide based gate dielectric layer, a first doped semiconductor layer, an interfacial dielectric layer, a high-k gate dielectric layer, a metal gate layer, and an optional semiconductor material layer in various device regions. The first gate stack may be employed to form a flash memory, and the second and third gate stacks may be employed to form a pair of p-type and n-type field effect transistors. | 10-15-2009 |
| 20090277670 | High Density Printed Circuit Board Interconnect and Method of Assembly - A printed circuit board assembly having an edge joined first and second sub-circuit board is provided. The first sub-circuit board includes an edge with a stair-step profile interconnection wherein each of the stairs on the profile exposes an area of a signal layer. Each exposed portion of the signal layer has a plurality of signal pads thereon. The second sub-circuit board includes an edge with an inverse stair-step profile interconnection. A pad-on-pad connector is positioned in-between and electrically interconnects the respective signal layers on each sub-circuit board. | 11-12-2009 |
| 20100032732 | ELECTRICAL ANTIFUSE HAVING A MULTI-THICKNESS DIELECTRIC LAYER - An electrical antifuse comprising a field effect transistor includes a gate dielectric having two gate dielectric portions. Upon application of electric field across the gate dielectric, the magnitude of the electrical field is locally enhanced at the boundary between the thick and thin gate dielectric portions due to the geometry, thereby allowing programming of the electrical antifuse at a lower supply voltage between the two electrodes, i.e., the body and the gate electrode of the transistor, across the gate dielectric. | 02-11-2010 |
| 20100181620 | STRUCTURE AND METHOD FOR FORMING PROGRAMMABLE HIGH-K/METAL GATE MEMORY DEVICE - A method of fabricating a memory device is provided that may begin with forming a layered gate stack overlying a semiconductor substrate and patterning a metal electrode layer stopping on the high-k gate dielectric layer of the layered gate stack to provide a first metal gate electrode and a second metal gate electrode on the semiconductor substrate. In a next process sequence, at least one spacer is formed on the first metal gate electrode overlying a portion of the high-k gate dielectric layer, wherein a remaining portion of the high-k gate dielectric is exposed. The remaining portion of the high-k gate dielectric layer is etched to provide a first high-k gate dielectric having a portion that extends beyond a sidewall of the first metal gate electrode and a second high-k gate dielectric having an edge that is aligned to a sidewall of the second metal gate electrode. | 07-22-2010 |
| 20100200949 | METHOD FOR TUNING THE THRESHOLD VOLTAGE OF A METAL GATE AND HIGH-K DEVICE - A method of forming a deep trench capacitor includes providing a wafer. Devices are formed on a front side of the wafer. A through-silicon-via is formed on a substrate of the wafer. Deep trenches are formed on a back side of the wafer. A deep trench capacitor is formed in the deep trench. The through-silicon-via connects the deep trench capacitor to the devices. | 08-12-2010 |
| 20100230781 | TRENCH ANTI-FUSE STRUCTURES FOR A PROGRAMMABLE INTEGRATED CIRCUIT - Trench anti-fuse structures, design structures embodied in a machine readable medium for designing, manufacturing, or testing a programmable integrated circuit. The anti-fuse structure includes a trench having a plurality of sidewalls that extend into a substrate, a doped region in the semiconductor material of the substrate proximate to the sidewalls of the trench, a conductive plug in the trench, and a dielectric layer on the sidewalls of the trench. The dielectric layer is disposed between the conductive plug and the doped region. The dielectric layer is configured so that a programming voltage applied between the doped region and the conductive plug causes a breakdown of the dielectric layer within a region of the trench. The trench sidewalls are arranged with a cross-sectional geometrical shape that is independent of position between a bottom wall of the deep trench and a top surface of the substrate. | 09-16-2010 |
| 20110031582 | FIN ANTI-FUSE WITH REDUCED PROGRAMMING VOLTAGE - A method forms an anti-fuse structure comprises a plurality of parallel conductive fins positioned on a substrate, each of the fins has a first end and a second end. A second electrical conductor is electrically connected to the second end of the fins. An insulator covers the first end of the fins and a first electrical conductor is positioned on the insulator. The first electrical conductor is electrically insulated from the first end of the fins by the insulator. The insulator is formed to a thickness sufficient to break down on the application of a predetermined voltage between the second electrical conductor and the first electrical conductor and thereby form an uninterrupted electrical connection between the second electrical conductor and the first electrical conductor through the fins. | 02-10-2011 |
