| Patent application number | Description | Published |
|---|
| 20080222584 | Method in a Computer-aided Design System for Generating a Functional Design Model of a Test Structure - A method in a computer-aided design system for generating a functional design model of a test structure. The test structure is used for performing device-specific testing and acquiring parametric data on integrated circuits, such that each chip generated from the functional design model is tested individually without excessive test time requirements, additional silicon, or special test equipment. The method includes a functional representation of a device test structure integrated into an IC design which tests a set of dummy devices that are identical or nearly identical to a selected set of functional representations of devices contained in the IC. The test structures are integrated from a device under test (DUT) library according to customer requirements and design requirements. The selected test structures are further prioritized and assigned to design elements within the design in order of priority. Placement algorithms use design, layout, and manufacturing requirements to place the selected test structures into the final layout of the design. | 09-11-2008 |
| 20080270951 | Embedded Test Circuit For Testing Integrated Circuits At The Die Level - A design structure instantiated in a machine readable medium; the design structure includes all of the necessary information for designing a test circuit. The test circuit is used for performing device-specific testing and acquiring parametric data on integrated circuits, for example ASICs, such that each chip is tested individually without excessive test time requirements, additional silicon, or special test equipment. The design structure includes at least one test circuit and may be integrated into an IC design, along with all of the required manufacturing data for producing a final design structure. The final design structure may be in the form of a GDS storage medium or another form of medium suitable for sending the final data structure to, for example, a manufacturer, foundry, customer, or other design house. | 10-30-2008 |
| 20080270954 | System for and Method of Integrating Test Structures into an Integrated Circuit - A system and method for performing device-specific testing and acquiring parametric data on integrated circuits, for example ASICs, such that each chip is tested individually without excessive test time requirements, additional silicon, or special test equipment. The testing system includes a device test structure integrated into unused backfill space in an IC design which tests a set of dummy devices that are identical to a selected set of devices contained in the IC. The device test structures are selected from a library according to customer requirements and design requirements. The selected test structures are further prioritized and assigned to design elements within the design in order of priority. Placement algorithms use design, layout, and manufacturing requirements to place the selected test structures into the final layout of the design to be manufactured. | 10-30-2008 |
| 20090001336 | PHASE CHANGE MATERIAL BASED TEMPERATURE SENSOR - A block of phase change material located in a semiconductor chip is reset to an amorphous state. The block of phase change material may be connected to an internal resistance measurement circuit that can transmit the measured resistance data to input/output pads either in an analog output format or in a digital output format. Depending on the ambient temperature, the resistance of the block of phase change material changes. By measuring a fractional resistance change compared to the resistance of the phase change material at a calibration temperature, the temperature of the region around the phase change material can be accurately measured. A logic decoder and an input/output circuit may be employed between the internal resistance measurement circuit and the input/output pads. A plurality of temperature sensing circuits containing phase change material blocks may be employed in the semiconductor chip to enable an accurate temperature profiling during chip operation. | 01-01-2009 |
| 20090039912 | Method of Acceptance for Semiconductor Devices - A method of accepting semiconductor chips is provided using on-chip parametric measurements. An on-chip parametric measurement structure is determined for each parameter in a set of parametric acceptance criteria. An on-chip parametric measurement macro is included in a design of each semiconductor chip for each identified on-chip parametric measurement structure. Each on-chip parametric measurement macro is tested to determine compliance of the semiconductor chip to the set of parametric acceptance criteria. Compliance to the set of parametric acceptance criteria is validated. | 02-12-2009 |
| 20090070722 | METHOD FOR GENERATING DEVICE MODEL OVERRIDES THROUGH THE USE OF ON-CHIP PARAMETRIC MEASUREMENT MACROS - A method generates area dependent design rules during semiconductor technology qualification by identifying the layout parametric variation in a semiconductor technology and establishing layout dependent design rules. This method applies the area dependent design rules to identify design sensitivity to area dependent design rules and to optimize semiconductor libraries and/or semiconductor products using an on-chip parametric monitor by designing processes for library elements, semiconductor design systems, and/or custom semiconductor products using the layout dependent design rules. | 03-12-2009 |
| 20090083690 | SYSTEM FOR AND METHOD OF INTEGRATING TEST STRUCTURES INTO AN INTEGRATED CIRCUIT - A system and method for performing device-specific testing and acquiring parametric data on integrated circuits, for example ASICs, such that each chip is tested individually without excessive test time requirements, additional silicon, or special test equipment. The testing system includes a device test structure integrated into an IC design which tests a set of dummy devices that are identical or nearly identical to a selected set of devices contained in the IC. The test structures are built from a device under test (DUT) library according to customer requirements and design requirements. The selected test structures are further prioritized and assigned to design elements within the design in order of priority. Placement algorithms use design, layout, and manufacturing requirements to place the selected test structures into the final layout of the design to be manufactured. | 03-26-2009 |
| 20090106712 | RELIABILITY EVALUATION AND SYSTEM FAIL WARNING METHODS USING ON CHIP PARAMETRIC MONITORS - A method of reliability evaluation and system fail warning using on chip parametric monitors. The method includes determining impact of parametric variation on reliability by identifying key parametric questions to be answered by stress, identifying parametric macros for each parameter, and identifying layout sensitive areas of evaluation. The process can also include a set of parametric macros in one of a test site or a product to be stressed, testing the set of parametric macros prior to start of stress and at each stress read out, and setting life time parameter profile for technology. | 04-23-2009 |
| 20090158444 | System and Method for Controlling Access to Addressable Integrated Circuits - A circuitry access system for controlling access to addressable circuit elements of an integrated circuit. The circuitry access system includes a first storage element having a first listing of unique identifiers each identifier representing one of the addressable circuit elements. A selector distinguishes a first subset of unique identifiers from the first listing. A second storage element receives and stores the first subset in an arrangement that does not include an indication of the absence of any unique identifier of the first listing that is not included in the first subset. An output of second storage element allows a user of the integrated circuit to access one or more of the addressable circuit elements corresponding to the first subset of unique identifiers. A method of controlling access to addressable circuit elements is also provided. | 06-18-2009 |
| 20090164961 | Design Structure for a System For Controlling Access to Addressable Integrated Circuits - A design structure for a circuitry access system for controlling access to addressable circuit elements of an integrated circuit. The circuitry access system includes a first storage element having a first listing of unique identifiers each identifier representing one of the addressable circuit elements. A selector distinguishes a first subset of unique identifiers from the first listing. A second storage element receives and stores the first subset in an arrangement that does not include an indication of the absence of any unique identifier of the first thing that is not included in the first subset. An output of second storage element allows a user of the integrated circuit to access one or more of the addressable circuit elements corresponding to the first subset of unique identifiers. | 06-25-2009 |
| 20090210201 | SYSTEM AND METHOD TO PREDICT CHIP IDDQ AND CONTROL LEAKAGE COMPONENTS - A method for predicting and controlling leakage wherein an IDDQ prediction macro is placed in a plurality of design topographies and data is collected using the IDDQ prediction macro. The IDDQ prediction macro is configured to measure subthreshold leakage and gate leakage for at least one device type in a semiconductor test site and in scribe lines using the IDDQ prediction macro and establish a leakage model. The method correlates the semiconductor test site measurements and the scribe line measurements to establish scribe line control limits, predicts product leakage; and sets subthreshold leakage limits and gate leakage limits for each product using the leakage model. | 08-20-2009 |
| 20090282375 | Circuit And Method Using Distributed Phase Change Elements For Across-Chip Temperature Profiling - Disclosed is an across-chip temperature sensing circuit and an associated method that can be used to profile the across-chip temperature gradient. The embodiments incorporate a plurality of phase change elements distributed approximately evenly across the semiconductor chip. These phase change elements are programmed to have essentially the same amorphous resistance. Temperature-dependent behavior exhibited by each of the phase change elements individually is compared to a reference (e.g., generated by a discrete reference phase change element, generated by another one of the phase change elements, or generated by an external reference) in order to profile the temperature gradient across the semiconductor chip. Once profiled, this temperature gradient can be used to redesign and/or relocate functional cores, to set stress limits for qualification of functional cores and/or to adjust operating specifications of functional cores. | 11-12-2009 |
| 20100254425 | PHASE CHANGE MATERIAL BASED TEMPERATURE SENSOR - A block of phase change material located in a semiconductor chip is reset to an amorphous state. The block of phase change material may be connected to an internal resistance measurement circuit that can transmit the measured resistance data to input/output pads either in an analog output format or in a digital output format. Depending on the ambient temperature, the resistance of the block of phase change material changes. By measuring a fractional resistance change compared to the resistance of the phase change material at a calibration temperature, the temperature of the region around the phase change material can be accurately measured. A logic decoder and an input/output circuit may be employed between the internal resistance measurement circuit and the input/output pads. A plurality of temperature sensing circuits containing phase change material blocks may be employed in the semiconductor chip to enable an accurate temperature profiling during chip operation. | 10-07-2010 |
